hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/edac/i5000_edac.c
....@@ -1134,8 +1134,6 @@
11341134 u32 actual_tolm;
11351135 u16 limit;
11361136 int slot_row;
1137
- int maxch;
1138
- int maxdimmperch;
11391137 int way0, way1;
11401138
11411139 pvt = mci->pvt_info;
....@@ -1144,9 +1142,6 @@
11441142 &pvt->u.ambase_bottom);
11451143 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
11461144 &pvt->u.ambase_top);
1147
-
1148
- maxdimmperch = pvt->maxdimmperch;
1149
- maxch = pvt->maxch;
11501145
11511146 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
11521147 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
....@@ -1253,7 +1248,7 @@
12531248 {
12541249 struct i5000_pvt *pvt;
12551250 struct dimm_info *dimm;
1256
- int empty, channel_count;
1251
+ int empty;
12571252 int max_csrows;
12581253 int mtr;
12591254 int csrow_megs;
....@@ -1261,8 +1256,6 @@
12611256 int slot;
12621257
12631258 pvt = mci->pvt_info;
1264
-
1265
- channel_count = pvt->maxch;
12661259 max_csrows = pvt->maxdimmperch * 2;
12671260
12681261 empty = 1; /* Assume NO memory */
....@@ -1282,9 +1275,8 @@
12821275 if (!MTR_DIMMS_PRESENT(mtr))
12831276 continue;
12841277
1285
- dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1286
- channel / MAX_BRANCHES,
1287
- channel % MAX_BRANCHES, slot);
1278
+ dimm = edac_get_dimm(mci, channel / MAX_BRANCHES,
1279
+ channel % MAX_BRANCHES, slot);
12881280
12891281 csrow_megs = pvt->dimm_info[slot][channel].megabytes;
12901282 dimm->grain = 8;
....@@ -1559,8 +1551,8 @@
15591551
15601552 edac_dbg(2, "MC:\n");
15611553
1562
- /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1563
- opstate_init();
1554
+ /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1555
+ opstate_init();
15641556
15651557 pci_rc = pci_register_driver(&i5000_driver);
15661558