add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/edac/amd64_edac.h
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@@ -96,6 +96,7 @@
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 /* Hardware limit on ChipSelect rows per MC and processors per system */
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 #define NUM_CHIPSELECTS			8
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 #define DRAM_RANGES			8
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+#define NUM_CONTROLLERS			8
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 #define ON true
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 #define OFF false
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@@ -119,6 +120,12 @@
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 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee
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 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490
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 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496
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+#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F0 0x1448
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+#define PCI_DEVICE_ID_AMD_17H_M60H_DF_F6 0x144e
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+#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440
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+#define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446
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+#define PCI_DEVICE_ID_AMD_19H_DF_F0	0x1650
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+#define PCI_DEVICE_ID_AMD_19H_DF_F6	0x1656
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 /*
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  * Function 1 - Address Map
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@@ -168,7 +175,8 @@
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 #define DCSM0				0x60
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 #define DCSM1				0x160
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-#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE)
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+#define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)
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+#define csrow_sec_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
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 #define DRAM_CONTROL			0x78
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@@ -258,7 +266,9 @@
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 /* UMC CH register offsets */
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 #define UMCCH_BASE_ADDR			0x0
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+#define UMCCH_BASE_ADDR_SEC		0x10
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 #define UMCCH_ADDR_MASK			0x20
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+#define UMCCH_ADDR_MASK_SEC		0x28
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 #define UMCCH_ADDR_CFG			0x30
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 #define UMCCH_DIMM_CFG			0x80
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 #define UMCCH_UMC_CFG			0x100
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@@ -274,8 +284,6 @@
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 #define UMC_SDP_INIT			BIT(31)
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-#define NUM_UMCS			2
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-
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 enum amd_families {
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 	K8_CPUS = 0,
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 	F10_CPUS,
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@@ -287,6 +295,9 @@
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 	F17_CPUS,
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 	F17_M10H_CPUS,
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 	F17_M30H_CPUS,
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+	F17_M60H_CPUS,
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+	F17_M70H_CPUS,
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+	F19_CPUS,
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 	NUM_FAMILIES,
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 };
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@@ -313,9 +324,11 @@
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 /* A DCT chip selects collection */
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 struct chip_select {
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 	u32 csbases[NUM_CHIPSELECTS];
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+	u32 csbases_sec[NUM_CHIPSELECTS];
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 	u8 b_cnt;
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 	u32 csmasks[NUM_CHIPSELECTS];
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+	u32 csmasks_sec[NUM_CHIPSELECTS];
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 	u8 m_cnt;
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 };
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@@ -353,8 +366,8 @@
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 	u32 dbam0;		/* DRAM Base Address Mapping reg for DCT0 */
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 	u32 dbam1;		/* DRAM Base Address Mapping reg for DCT1 */
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-	/* one for each DCT */
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-	struct chip_select csels[2];
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+	/* one for each DCT/UMC */
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+	struct chip_select csels[NUM_CONTROLLERS];
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 	/* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */
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 	struct dram_range ranges[DRAM_RANGES];
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@@ -366,7 +379,7 @@
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 	u32 dct_sel_hi;		/* DRAM Controller Select High */
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 	u32 online_spare;	/* On-Line spare Reg */
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-	/* x4 or x8 syndromes in use */
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+	/* x4, x8, or x16 syndromes in use */
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 	u8 ecc_sym_sz;
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 	/* place to store error injection parameters prior to issue */
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@@ -399,8 +412,8 @@
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 static inline u32 get_umc_base(u8 channel)
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 {
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-	/* ch0: 0x50000, ch1: 0x150000 */
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-	return 0x50000 + (!!channel << 20);
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+	/* chY: 0xY50000 */
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+	return 0x50000 + (channel << 20);
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 }
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 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
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@@ -472,6 +485,8 @@
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 struct amd64_family_type {
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 	const char *ctl_name;
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 	u16 f0_id, f1_id, f2_id, f6_id;
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+	/* Maximum number of memory controllers per die/node. */
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+	u8 max_mcs;
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 	struct low_ops ops;
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 };
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