.. | .. |
---|
| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
---|
1 | 2 | /* |
---|
2 | 3 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. |
---|
3 | | - * |
---|
4 | | - * This program is free software; you can redistribute it and/or modify it |
---|
5 | | - * under the terms of the GNU General Public License as published by the Free |
---|
6 | | - * Software Foundation; either version 2 of the License, or (at your option) |
---|
7 | | - * any later version. |
---|
8 | | - * |
---|
9 | | - * This program is distributed in the hope that it will be useful, but WITHOUT |
---|
10 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
---|
11 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
---|
12 | | - * more details. |
---|
13 | | - * |
---|
14 | | - * The full GNU General Public License is included in this distribution in the |
---|
15 | | - * file called COPYING. |
---|
16 | 4 | */ |
---|
17 | 5 | #ifndef _IOAT_REGISTERS_H_ |
---|
18 | 6 | #define _IOAT_REGISTERS_H_ |
---|
.. | .. |
---|
84 | 72 | #define IOAT_CAP_PQ 0x00000200 |
---|
85 | 73 | #define IOAT_CAP_DWBES 0x00002000 |
---|
86 | 74 | #define IOAT_CAP_RAID16SS 0x00020000 |
---|
| 75 | +#define IOAT_CAP_DPS 0x00800000 |
---|
| 76 | + |
---|
| 77 | +#define IOAT_PREFETCH_LIMIT_OFFSET 0x4C /* CHWPREFLMT */ |
---|
87 | 78 | |
---|
88 | 79 | #define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */ |
---|
89 | 80 | |
---|
.. | .. |
---|
243 | 234 | |
---|
244 | 235 | #define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */ |
---|
245 | 236 | |
---|
| 237 | +#define IOAT_CHAN_DRSCTL_OFFSET 0xB6 |
---|
| 238 | +#define IOAT_CHAN_DRSZ_4KB 0x0000 |
---|
| 239 | +#define IOAT_CHAN_DRSZ_8KB 0x0001 |
---|
| 240 | +#define IOAT_CHAN_DRSZ_2MB 0x0009 |
---|
| 241 | +#define IOAT_CHAN_DRS_EN 0x0100 |
---|
| 242 | +#define IOAT_CHAN_DRS_AUTOWRAP 0x0200 |
---|
| 243 | + |
---|
| 244 | +#define IOAT_CHAN_LTR_SWSEL_OFFSET 0xBC |
---|
| 245 | +#define IOAT_CHAN_LTR_SWSEL_ACTIVE 0x0 |
---|
| 246 | +#define IOAT_CHAN_LTR_SWSEL_IDLE 0x1 |
---|
| 247 | + |
---|
| 248 | +#define IOAT_CHAN_LTR_ACTIVE_OFFSET 0xC0 |
---|
| 249 | +#define IOAT_CHAN_LTR_ACTIVE_SNVAL 0x0000 /* 0 us */ |
---|
| 250 | +#define IOAT_CHAN_LTR_ACTIVE_SNLATSCALE 0x0800 /* 1us scale */ |
---|
| 251 | +#define IOAT_CHAN_LTR_ACTIVE_SNREQMNT 0x8000 /* snoop req enable */ |
---|
| 252 | + |
---|
| 253 | +#define IOAT_CHAN_LTR_IDLE_OFFSET 0xC4 |
---|
| 254 | +#define IOAT_CHAN_LTR_IDLE_SNVAL 0x0258 /* 600 us */ |
---|
| 255 | +#define IOAT_CHAN_LTR_IDLE_SNLATSCALE 0x0800 /* 1us scale */ |
---|
| 256 | +#define IOAT_CHAN_LTR_IDLE_SNREQMNT 0x8000 /* snoop req enable */ |
---|
| 257 | + |
---|
246 | 258 | #endif /* _IOAT_REGISTERS_H_ */ |
---|