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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/dma/dma-jz4780.c
....@@ -1,13 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Ingenic JZ4780 DMA controller
34  *
45  * Copyright (c) 2015 Imagination Technologies
56  * Author: Alex Smith <alex@alex-smith.me.uk>
6
- *
7
- * This program is free software; you can redistribute it and/or modify it
8
- * under the terms of the GNU General Public License as published by the
9
- * Free Software Foundation;  either version 2 of the  License, or (at your
10
- * option) any later version.
117  */
128 
139 #include <linux/clk.h>
....@@ -16,6 +12,7 @@
1612 #include <linux/interrupt.h>
1713 #include <linux/module.h>
1814 #include <linux/of.h>
15
+#include <linux/of_device.h>
1916 #include <linux/of_dma.h>
2017 #include <linux/platform_device.h>
2118 #include <linux/slab.h>
....@@ -23,33 +20,35 @@
2320 #include "dmaengine.h"
2421 #include "virt-dma.h"
2522 
26
-#define JZ_DMA_NR_CHANNELS	32
27
-
2823 /* Global registers. */
29
-#define JZ_DMA_REG_DMAC		0x1000
30
-#define JZ_DMA_REG_DIRQP	0x1004
31
-#define JZ_DMA_REG_DDR		0x1008
32
-#define JZ_DMA_REG_DDRS		0x100c
33
-#define JZ_DMA_REG_DMACP	0x101c
34
-#define JZ_DMA_REG_DSIRQP	0x1020
35
-#define JZ_DMA_REG_DSIRQM	0x1024
36
-#define JZ_DMA_REG_DCIRQP	0x1028
37
-#define JZ_DMA_REG_DCIRQM	0x102c
24
+#define JZ_DMA_REG_DMAC		0x00
25
+#define JZ_DMA_REG_DIRQP	0x04
26
+#define JZ_DMA_REG_DDR		0x08
27
+#define JZ_DMA_REG_DDRS		0x0c
28
+#define JZ_DMA_REG_DCKE		0x10
29
+#define JZ_DMA_REG_DCKES	0x14
30
+#define JZ_DMA_REG_DCKEC	0x18
31
+#define JZ_DMA_REG_DMACP	0x1c
32
+#define JZ_DMA_REG_DSIRQP	0x20
33
+#define JZ_DMA_REG_DSIRQM	0x24
34
+#define JZ_DMA_REG_DCIRQP	0x28
35
+#define JZ_DMA_REG_DCIRQM	0x2c
3836 
3937 /* Per-channel registers. */
4038 #define JZ_DMA_REG_CHAN(n)	(n * 0x20)
41
-#define JZ_DMA_REG_DSA(n)	(0x00 + JZ_DMA_REG_CHAN(n))
42
-#define JZ_DMA_REG_DTA(n)	(0x04 + JZ_DMA_REG_CHAN(n))
43
-#define JZ_DMA_REG_DTC(n)	(0x08 + JZ_DMA_REG_CHAN(n))
44
-#define JZ_DMA_REG_DRT(n)	(0x0c + JZ_DMA_REG_CHAN(n))
45
-#define JZ_DMA_REG_DCS(n)	(0x10 + JZ_DMA_REG_CHAN(n))
46
-#define JZ_DMA_REG_DCM(n)	(0x14 + JZ_DMA_REG_CHAN(n))
47
-#define JZ_DMA_REG_DDA(n)	(0x18 + JZ_DMA_REG_CHAN(n))
48
-#define JZ_DMA_REG_DSD(n)	(0x1c + JZ_DMA_REG_CHAN(n))
39
+#define JZ_DMA_REG_DSA		0x00
40
+#define JZ_DMA_REG_DTA		0x04
41
+#define JZ_DMA_REG_DTC		0x08
42
+#define JZ_DMA_REG_DRT		0x0c
43
+#define JZ_DMA_REG_DCS		0x10
44
+#define JZ_DMA_REG_DCM		0x14
45
+#define JZ_DMA_REG_DDA		0x18
46
+#define JZ_DMA_REG_DSD		0x1c
4947 
5048 #define JZ_DMA_DMAC_DMAE	BIT(0)
5149 #define JZ_DMA_DMAC_AR		BIT(2)
5250 #define JZ_DMA_DMAC_HLT		BIT(3)
51
+#define JZ_DMA_DMAC_FAIC	BIT(27)
5352 #define JZ_DMA_DMAC_FMSC	BIT(31)
5453 
5554 #define JZ_DMA_DRT_AUTO		0x8
....@@ -86,6 +85,15 @@
8685 				 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
8786 				 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
8887 
88
+#define JZ4780_DMA_CTRL_OFFSET	0x1000
89
+
90
+/* macros for use with jz4780_dma_soc_data.flags */
91
+#define JZ_SOC_DATA_ALLOW_LEGACY_DT	BIT(0)
92
+#define JZ_SOC_DATA_PROGRAMMABLE_DMA	BIT(1)
93
+#define JZ_SOC_DATA_PER_CHAN_PM		BIT(2)
94
+#define JZ_SOC_DATA_NO_DCKES_DCKEC	BIT(3)
95
+#define JZ_SOC_DATA_BREAK_LINKS		BIT(4)
96
+
8997 /**
9098  * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
9199  * @dcm: value for the DCM (channel command) register
....@@ -94,17 +102,12 @@
94102  * @dtc: transfer count (number of blocks of the transfer size specified in DCM
95103  * to transfer) in the low 24 bits, offset of the next descriptor from the
96104  * descriptor base address in the upper 8 bits.
97
- * @sd: target/source stride difference (in stride transfer mode).
98
- * @drt: request type
99105  */
100106 struct jz4780_dma_hwdesc {
101107 	uint32_t dcm;
102108 	uint32_t dsa;
103109 	uint32_t dta;
104110 	uint32_t dtc;
105
-	uint32_t sd;
106
-	uint32_t drt;
107
-	uint32_t reserved[2];
108111 };
109112 
110113 /* Size of allocations for hardware descriptor blocks. */
....@@ -135,18 +138,25 @@
135138 	unsigned int curr_hwdesc;
136139 };
137140 
141
+struct jz4780_dma_soc_data {
142
+	unsigned int nb_channels;
143
+	unsigned int transfer_ord_max;
144
+	unsigned long flags;
145
+};
146
+
138147 struct jz4780_dma_dev {
139148 	struct dma_device dma_device;
140
-	void __iomem *base;
149
+	void __iomem *chn_base;
150
+	void __iomem *ctrl_base;
141151 	struct clk *clk;
142152 	unsigned int irq;
153
+	const struct jz4780_dma_soc_data *soc_data;
143154 
144155 	uint32_t chan_reserved;
145
-	struct jz4780_dma_chan chan[JZ_DMA_NR_CHANNELS];
156
+	struct jz4780_dma_chan chan[];
146157 };
147158 
148159 struct jz4780_dma_filter_data {
149
-	struct device_node *of_node;
150160 	uint32_t transfer_type;
151161 	int channel;
152162 };
....@@ -169,16 +179,51 @@
169179 			    dma_device);
170180 }
171181 
172
-static inline uint32_t jz4780_dma_readl(struct jz4780_dma_dev *jzdma,
173
-	unsigned int reg)
182
+static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma,
183
+	unsigned int chn, unsigned int reg)
174184 {
175
-	return readl(jzdma->base + reg);
185
+	return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
176186 }
177187 
178
-static inline void jz4780_dma_writel(struct jz4780_dma_dev *jzdma,
188
+static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev *jzdma,
189
+	unsigned int chn, unsigned int reg, uint32_t val)
190
+{
191
+	writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
192
+}
193
+
194
+static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma,
195
+	unsigned int reg)
196
+{
197
+	return readl(jzdma->ctrl_base + reg);
198
+}
199
+
200
+static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma,
179201 	unsigned int reg, uint32_t val)
180202 {
181
-	writel(val, jzdma->base + reg);
203
+	writel(val, jzdma->ctrl_base + reg);
204
+}
205
+
206
+static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma,
207
+	unsigned int chn)
208
+{
209
+	if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) {
210
+		unsigned int reg;
211
+
212
+		if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)
213
+			reg = JZ_DMA_REG_DCKE;
214
+		else
215
+			reg = JZ_DMA_REG_DCKES;
216
+
217
+		jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn));
218
+	}
219
+}
220
+
221
+static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma,
222
+	unsigned int chn)
223
+{
224
+	if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) &&
225
+			!(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC))
226
+		jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn));
182227 }
183228 
184229 static struct jz4780_dma_desc *jz4780_dma_desc_alloc(
....@@ -215,8 +260,10 @@
215260 	kfree(desc);
216261 }
217262 
218
-static uint32_t jz4780_dma_transfer_size(unsigned long val, uint32_t *shift)
263
+static uint32_t jz4780_dma_transfer_size(struct jz4780_dma_chan *jzchan,
264
+	unsigned long val, uint32_t *shift)
219265 {
266
+	struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
220267 	int ord = ffs(val) - 1;
221268 
222269 	/*
....@@ -228,8 +275,8 @@
228275 	 */
229276 	if (ord == 3)
230277 		ord = 2;
231
-	else if (ord > 7)
232
-		ord = 7;
278
+	else if (ord > jzdma->soc_data->transfer_ord_max)
279
+		ord = jzdma->soc_data->transfer_ord_max;
233280 
234281 	*shift = ord;
235282 
....@@ -262,7 +309,6 @@
262309 		desc->dcm = JZ_DMA_DCM_SAI;
263310 		desc->dsa = addr;
264311 		desc->dta = config->dst_addr;
265
-		desc->drt = jzchan->transfer_type;
266312 
267313 		width = config->dst_addr_width;
268314 		maxburst = config->dst_maxburst;
....@@ -270,7 +316,6 @@
270316 		desc->dcm = JZ_DMA_DCM_DAI;
271317 		desc->dsa = config->src_addr;
272318 		desc->dta = addr;
273
-		desc->drt = jzchan->transfer_type;
274319 
275320 		width = config->src_addr_width;
276321 		maxburst = config->src_maxburst;
....@@ -283,7 +328,7 @@
283328 	 * divisible by the transfer size, and we must not use more than the
284329 	 * maximum burst specified by the user.
285330 	 */
286
-	tsz = jz4780_dma_transfer_size(addr | len | (width * maxburst),
331
+	tsz = jz4780_dma_transfer_size(jzchan, addr | len | (width * maxburst),
287332 				       &jzchan->transfer_shift);
288333 
289334 	switch (width) {
....@@ -311,6 +356,7 @@
311356 	void *context)
312357 {
313358 	struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
359
+	struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
314360 	struct jz4780_dma_desc *desc;
315361 	unsigned int i;
316362 	int err;
....@@ -331,7 +377,8 @@
331377 
332378 		desc->desc[i].dcm |= JZ_DMA_DCM_TIE;
333379 
334
-		if (i != (sg_len - 1)) {
380
+		if (i != (sg_len - 1) &&
381
+		    !(jzdma->soc_data->flags & JZ_SOC_DATA_BREAK_LINKS)) {
335382 			/* Automatically proceeed to the next descriptor. */
336383 			desc->desc[i].dcm |= JZ_DMA_DCM_LINK;
337384 
....@@ -412,12 +459,13 @@
412459 	if (!desc)
413460 		return NULL;
414461 
415
-	tsz = jz4780_dma_transfer_size(dest | src | len,
462
+	tsz = jz4780_dma_transfer_size(jzchan, dest | src | len,
416463 				       &jzchan->transfer_shift);
464
+
465
+	jzchan->transfer_type = JZ_DMA_DRT_AUTO;
417466 
418467 	desc->desc[0].dsa = src;
419468 	desc->desc[0].dta = dest;
420
-	desc->desc[0].drt = JZ_DMA_DRT_AUTO;
421469 	desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI |
422470 			    tsz << JZ_DMA_DCM_TSZ_SHIFT |
423471 			    JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT |
....@@ -472,18 +520,34 @@
472520 			(jzchan->curr_hwdesc + 1) % jzchan->desc->count;
473521 	}
474522 
475
-	/* Use 8-word descriptors. */
476
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), JZ_DMA_DCS_DES8);
523
+	/* Enable the channel's clock. */
524
+	jz4780_dma_chan_enable(jzdma, jzchan->id);
525
+
526
+	/* Use 4-word descriptors. */
527
+	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
528
+
529
+	/* Set transfer type. */
530
+	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT,
531
+			      jzchan->transfer_type);
532
+
533
+	/*
534
+	 * Set the transfer count. This is redundant for a descriptor-driven
535
+	 * transfer. However, there can be a delay between the transfer start
536
+	 * time and when DTCn reg contains the new transfer count. Setting
537
+	 * it explicitly ensures residue is computed correctly at all times.
538
+	 */
539
+	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC,
540
+				jzchan->desc->desc[jzchan->curr_hwdesc].dtc);
477541 
478542 	/* Write descriptor address and initiate descriptor fetch. */
479543 	desc_phys = jzchan->desc->desc_phys +
480544 		    (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));
481
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DDA(jzchan->id), desc_phys);
482
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
545
+	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DDA, desc_phys);
546
+	jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
483547 
484548 	/* Enable the channel. */
485
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id),
486
-			  JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE);
549
+	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS,
550
+			      JZ_DMA_DCS_CTE);
487551 }
488552 
489553 static void jz4780_dma_issue_pending(struct dma_chan *chan)
....@@ -509,11 +573,13 @@
509573 	spin_lock_irqsave(&jzchan->vchan.lock, flags);
510574 
511575 	/* Clear the DMA status and stop the transfer. */
512
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0);
576
+	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
513577 	if (jzchan->desc) {
514578 		vchan_terminate_vdesc(&jzchan->desc->vdesc);
515579 		jzchan->desc = NULL;
516580 	}
581
+
582
+	jz4780_dma_chan_disable(jzdma, jzchan->id);
517583 
518584 	vchan_get_all_descriptors(&jzchan->vchan, &head);
519585 
....@@ -526,8 +592,10 @@
526592 static void jz4780_dma_synchronize(struct dma_chan *chan)
527593 {
528594 	struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
595
+	struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
529596 
530597 	vchan_synchronize(&jzchan->vchan);
598
+	jz4780_dma_chan_disable(jzdma, jzchan->id);
531599 }
532600 
533601 static int jz4780_dma_config(struct dma_chan *chan,
....@@ -549,21 +617,17 @@
549617 	struct jz4780_dma_desc *desc, unsigned int next_sg)
550618 {
551619 	struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
552
-	unsigned int residue, count;
620
+	unsigned int count = 0;
553621 	unsigned int i;
554622 
555
-	residue = 0;
556
-
557623 	for (i = next_sg; i < desc->count; i++)
558
-		residue += desc->desc[i].dtc << jzchan->transfer_shift;
624
+		count += desc->desc[i].dtc & GENMASK(23, 0);
559625 
560
-	if (next_sg != 0) {
561
-		count = jz4780_dma_readl(jzdma,
562
-					 JZ_DMA_REG_DTC(jzchan->id));
563
-		residue += count << jzchan->transfer_shift;
564
-	}
626
+	if (next_sg != 0)
627
+		count += jz4780_dma_chn_readl(jzdma, jzchan->id,
628
+					 JZ_DMA_REG_DTC);
565629 
566
-	return residue;
630
+	return count << jzchan->transfer_shift;
567631 }
568632 
569633 static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan,
....@@ -573,6 +637,7 @@
573637 	struct virt_dma_desc *vdesc;
574638 	enum dma_status status;
575639 	unsigned long flags;
640
+	unsigned long residue = 0;
576641 
577642 	spin_lock_irqsave(&jzchan->vchan.lock, flags);
578643 
....@@ -583,13 +648,13 @@
583648 	vdesc = vchan_find_desc(&jzchan->vchan, cookie);
584649 	if (vdesc) {
585650 		/* On the issued list, so hasn't been processed yet */
586
-		txstate->residue = jz4780_dma_desc_residue(jzchan,
651
+		residue = jz4780_dma_desc_residue(jzchan,
587652 					to_jz4780_dma_desc(vdesc), 0);
588653 	} else if (cookie == jzchan->desc->vdesc.tx.cookie) {
589
-		txstate->residue = jz4780_dma_desc_residue(jzchan, jzchan->desc,
654
+		residue = jz4780_dma_desc_residue(jzchan, jzchan->desc,
590655 					jzchan->curr_hwdesc + 1);
591
-	} else
592
-		txstate->residue = 0;
656
+	}
657
+	dma_set_residue(txstate, residue);
593658 
594659 	if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc
595660 	    && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT))
....@@ -600,15 +665,18 @@
600665 	return status;
601666 }
602667 
603
-static void jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
604
-	struct jz4780_dma_chan *jzchan)
668
+static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
669
+				struct jz4780_dma_chan *jzchan)
605670 {
671
+	const unsigned int soc_flags = jzdma->soc_data->flags;
672
+	struct jz4780_dma_desc *desc = jzchan->desc;
606673 	uint32_t dcs;
674
+	bool ack = true;
607675 
608676 	spin_lock(&jzchan->vchan.lock);
609677 
610
-	dcs = jz4780_dma_readl(jzdma, JZ_DMA_REG_DCS(jzchan->id));
611
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0);
678
+	dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS);
679
+	jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
612680 
613681 	if (dcs & JZ_DMA_DCS_AR) {
614682 		dev_warn(&jzchan->vchan.chan.dev->device,
....@@ -626,12 +694,23 @@
626694 		if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) {
627695 			if (jzchan->desc->type == DMA_CYCLIC) {
628696 				vchan_cyclic_callback(&jzchan->desc->vdesc);
629
-			} else {
630
-				vchan_cookie_complete(&jzchan->desc->vdesc);
631
-				jzchan->desc = NULL;
632
-			}
633697 
634
-			jz4780_dma_begin(jzchan);
698
+				jz4780_dma_begin(jzchan);
699
+			} else if (dcs & JZ_DMA_DCS_TT) {
700
+				if (!(soc_flags & JZ_SOC_DATA_BREAK_LINKS) ||
701
+				    (jzchan->curr_hwdesc + 1 == desc->count)) {
702
+					vchan_cookie_complete(&desc->vdesc);
703
+					jzchan->desc = NULL;
704
+				}
705
+
706
+				jz4780_dma_begin(jzchan);
707
+			} else {
708
+				/* False positive - continue the transfer */
709
+				ack = false;
710
+				jz4780_dma_chn_writel(jzdma, jzchan->id,
711
+						      JZ_DMA_REG_DCS,
712
+						      JZ_DMA_DCS_CTE);
713
+			}
635714 		}
636715 	} else {
637716 		dev_err(&jzchan->vchan.chan.dev->device,
....@@ -639,30 +718,32 @@
639718 	}
640719 
641720 	spin_unlock(&jzchan->vchan.lock);
721
+
722
+	return ack;
642723 }
643724 
644725 static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
645726 {
646727 	struct jz4780_dma_dev *jzdma = data;
647
-	uint32_t pending, dmac;
728
+	unsigned int nb_channels = jzdma->soc_data->nb_channels;
729
+	unsigned long pending;
730
+	uint32_t dmac;
648731 	int i;
649732 
650
-	pending = jz4780_dma_readl(jzdma, JZ_DMA_REG_DIRQP);
733
+	pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP);
651734 
652
-	for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) {
653
-		if (!(pending & (1<<i)))
654
-			continue;
655
-
656
-		jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]);
735
+	for_each_set_bit(i, &pending, nb_channels) {
736
+		if (jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]))
737
+			pending &= ~BIT(i);
657738 	}
658739 
659740 	/* Clear halt and address error status of all channels. */
660
-	dmac = jz4780_dma_readl(jzdma, JZ_DMA_REG_DMAC);
741
+	dmac = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DMAC);
661742 	dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR);
662
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
743
+	jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
663744 
664745 	/* Clear interrupt pending status. */
665
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DIRQP, 0);
746
+	jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, pending);
666747 
667748 	return IRQ_HANDLED;
668749 }
....@@ -699,8 +780,6 @@
699780 	struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
700781 	struct jz4780_dma_filter_data *data = param;
701782 
702
-	if (jzdma->dma_device.dev->of_node != data->of_node)
703
-		return false;
704783 
705784 	if (data->channel > -1) {
706785 		if (data->channel != jzchan->id)
....@@ -724,12 +803,11 @@
724803 	if (dma_spec->args_count != 2)
725804 		return NULL;
726805 
727
-	data.of_node = ofdma->of_node;
728806 	data.transfer_type = dma_spec->args[0];
729807 	data.channel = dma_spec->args[1];
730808 
731809 	if (data.channel > -1) {
732
-		if (data.channel >= JZ_DMA_NR_CHANNELS) {
810
+		if (data.channel >= jzdma->soc_data->nb_channels) {
733811 			dev_err(jzdma->dma_device.dev,
734812 				"device requested non-existent channel %u\n",
735813 				data.channel);
....@@ -749,13 +827,15 @@
749827 		return dma_get_slave_channel(
750828 			&jzdma->chan[data.channel].vchan.chan);
751829 	} else {
752
-		return dma_request_channel(mask, jz4780_dma_filter_fn, &data);
830
+		return __dma_request_channel(&mask, jz4780_dma_filter_fn, &data,
831
+					     ofdma->of_node);
753832 	}
754833 }
755834 
756835 static int jz4780_dma_probe(struct platform_device *pdev)
757836 {
758837 	struct device *dev = &pdev->dev;
838
+	const struct jz4780_dma_soc_data *soc_data;
759839 	struct jz4780_dma_dev *jzdma;
760840 	struct jz4780_dma_chan *jzchan;
761841 	struct dma_device *dd;
....@@ -767,42 +847,44 @@
767847 		return -EINVAL;
768848 	}
769849 
770
-	jzdma = devm_kzalloc(dev, sizeof(*jzdma), GFP_KERNEL);
850
+	soc_data = device_get_match_data(dev);
851
+	if (!soc_data)
852
+		return -EINVAL;
853
+
854
+	jzdma = devm_kzalloc(dev, struct_size(jzdma, chan,
855
+			     soc_data->nb_channels), GFP_KERNEL);
771856 	if (!jzdma)
772857 		return -ENOMEM;
773858 
859
+	jzdma->soc_data = soc_data;
774860 	platform_set_drvdata(pdev, jzdma);
775861 
776
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
777
-	if (!res) {
862
+	jzdma->chn_base = devm_platform_ioremap_resource(pdev, 0);
863
+	if (IS_ERR(jzdma->chn_base))
864
+		return PTR_ERR(jzdma->chn_base);
865
+
866
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
867
+	if (res) {
868
+		jzdma->ctrl_base = devm_ioremap_resource(dev, res);
869
+		if (IS_ERR(jzdma->ctrl_base))
870
+			return PTR_ERR(jzdma->ctrl_base);
871
+	} else if (soc_data->flags & JZ_SOC_DATA_ALLOW_LEGACY_DT) {
872
+		/*
873
+		 * On JZ4780, if the second memory resource was not supplied,
874
+		 * assume we're using an old devicetree, and calculate the
875
+		 * offset to the control registers.
876
+		 */
877
+		jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET;
878
+	} else {
778879 		dev_err(dev, "failed to get I/O memory\n");
779880 		return -EINVAL;
780
-	}
781
-
782
-	jzdma->base = devm_ioremap_resource(dev, res);
783
-	if (IS_ERR(jzdma->base))
784
-		return PTR_ERR(jzdma->base);
785
-
786
-	ret = platform_get_irq(pdev, 0);
787
-	if (ret < 0) {
788
-		dev_err(dev, "failed to get IRQ: %d\n", ret);
789
-		return ret;
790
-	}
791
-
792
-	jzdma->irq = ret;
793
-
794
-	ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev),
795
-			  jzdma);
796
-	if (ret) {
797
-		dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
798
-		return ret;
799881 	}
800882 
801883 	jzdma->clk = devm_clk_get(dev, NULL);
802884 	if (IS_ERR(jzdma->clk)) {
803885 		dev_err(dev, "failed to get clock\n");
804886 		ret = PTR_ERR(jzdma->clk);
805
-		goto err_free_irq;
887
+		return ret;
806888 	}
807889 
808890 	clk_prepare_enable(jzdma->clk);
....@@ -839,13 +921,15 @@
839921 	 * Also set the FMSC bit - it increases MSC performance, so it makes
840922 	 * little sense not to enable it.
841923 	 */
842
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC,
843
-			  JZ_DMA_DMAC_DMAE | JZ_DMA_DMAC_FMSC);
844
-	jz4780_dma_writel(jzdma, JZ_DMA_REG_DMACP, 0);
924
+	jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, JZ_DMA_DMAC_DMAE |
925
+			       JZ_DMA_DMAC_FAIC | JZ_DMA_DMAC_FMSC);
926
+
927
+	if (soc_data->flags & JZ_SOC_DATA_PROGRAMMABLE_DMA)
928
+		jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMACP, 0);
845929 
846930 	INIT_LIST_HEAD(&dd->channels);
847931 
848
-	for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) {
932
+	for (i = 0; i < soc_data->nb_channels; i++) {
849933 		jzchan = &jzdma->chan[i];
850934 		jzchan->id = i;
851935 
....@@ -853,10 +937,23 @@
853937 		jzchan->vchan.desc_free = jz4780_dma_desc_free;
854938 	}
855939 
856
-	ret = dma_async_device_register(dd);
940
+	ret = platform_get_irq(pdev, 0);
941
+	if (ret < 0)
942
+		goto err_disable_clk;
943
+
944
+	jzdma->irq = ret;
945
+
946
+	ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev),
947
+			  jzdma);
948
+	if (ret) {
949
+		dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
950
+		goto err_disable_clk;
951
+	}
952
+
953
+	ret = dmaenginem_async_device_register(dd);
857954 	if (ret) {
858955 		dev_err(dev, "failed to register device\n");
859
-		goto err_disable_clk;
956
+		goto err_free_irq;
860957 	}
861958 
862959 	/* Register with OF DMA helpers. */
....@@ -864,20 +961,17 @@
864961 					 jzdma);
865962 	if (ret) {
866963 		dev_err(dev, "failed to register OF DMA controller\n");
867
-		goto err_unregister_dev;
964
+		goto err_free_irq;
868965 	}
869966 
870967 	dev_info(dev, "JZ4780 DMA controller initialised\n");
871968 	return 0;
872969 
873
-err_unregister_dev:
874
-	dma_async_device_unregister(dd);
970
+err_free_irq:
971
+	free_irq(jzdma->irq, jzdma);
875972 
876973 err_disable_clk:
877974 	clk_disable_unprepare(jzdma->clk);
878
-
879
-err_free_irq:
880
-	free_irq(jzdma->irq, jzdma);
881975 	return ret;
882976 }
883977 
....@@ -888,17 +982,59 @@
888982 
889983 	of_dma_controller_free(pdev->dev.of_node);
890984 
985
+	clk_disable_unprepare(jzdma->clk);
891986 	free_irq(jzdma->irq, jzdma);
892987 
893
-	for (i = 0; i < JZ_DMA_NR_CHANNELS; i++)
988
+	for (i = 0; i < jzdma->soc_data->nb_channels; i++)
894989 		tasklet_kill(&jzdma->chan[i].vchan.task);
895990 
896
-	dma_async_device_unregister(&jzdma->dma_device);
897991 	return 0;
898992 }
899993 
994
+static const struct jz4780_dma_soc_data jz4740_dma_soc_data = {
995
+	.nb_channels = 6,
996
+	.transfer_ord_max = 5,
997
+	.flags = JZ_SOC_DATA_BREAK_LINKS,
998
+};
999
+
1000
+static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = {
1001
+	.nb_channels = 6,
1002
+	.transfer_ord_max = 5,
1003
+	.flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC |
1004
+		 JZ_SOC_DATA_BREAK_LINKS,
1005
+};
1006
+
1007
+static const struct jz4780_dma_soc_data jz4770_dma_soc_data = {
1008
+	.nb_channels = 6,
1009
+	.transfer_ord_max = 6,
1010
+	.flags = JZ_SOC_DATA_PER_CHAN_PM,
1011
+};
1012
+
1013
+static const struct jz4780_dma_soc_data jz4780_dma_soc_data = {
1014
+	.nb_channels = 32,
1015
+	.transfer_ord_max = 7,
1016
+	.flags = JZ_SOC_DATA_ALLOW_LEGACY_DT | JZ_SOC_DATA_PROGRAMMABLE_DMA,
1017
+};
1018
+
1019
+static const struct jz4780_dma_soc_data x1000_dma_soc_data = {
1020
+	.nb_channels = 8,
1021
+	.transfer_ord_max = 7,
1022
+	.flags = JZ_SOC_DATA_PROGRAMMABLE_DMA,
1023
+};
1024
+
1025
+static const struct jz4780_dma_soc_data x1830_dma_soc_data = {
1026
+	.nb_channels = 32,
1027
+	.transfer_ord_max = 7,
1028
+	.flags = JZ_SOC_DATA_PROGRAMMABLE_DMA,
1029
+};
1030
+
9001031 static const struct of_device_id jz4780_dma_dt_match[] = {
901
-	{ .compatible = "ingenic,jz4780-dma", .data = NULL },
1032
+	{ .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data },
1033
+	{ .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data },
1034
+	{ .compatible = "ingenic,jz4770-dma", .data = &jz4770_dma_soc_data },
1035
+	{ .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data },
1036
+	{ .compatible = "ingenic,x1000-dma", .data = &x1000_dma_soc_data },
1037
+	{ .compatible = "ingenic,x1830-dma", .data = &x1830_dma_soc_data },
9021038 	{},
9031039 };
9041040 MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match);