.. | .. |
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1 | | -/* |
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2 | | - This file is provided under a dual BSD/GPLv2 license. When using or |
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3 | | - redistributing this file, you may do so under either license. |
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4 | | - |
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5 | | - GPL LICENSE SUMMARY |
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6 | | - Copyright(c) 2014 Intel Corporation. |
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7 | | - This program is free software; you can redistribute it and/or modify |
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8 | | - it under the terms of version 2 of the GNU General Public License as |
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9 | | - published by the Free Software Foundation. |
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10 | | - |
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11 | | - This program is distributed in the hope that it will be useful, but |
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12 | | - WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | | - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | | - General Public License for more details. |
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15 | | - |
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16 | | - Contact Information: |
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17 | | - qat-linux@intel.com |
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18 | | - |
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19 | | - BSD LICENSE |
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20 | | - Copyright(c) 2014 Intel Corporation. |
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21 | | - Redistribution and use in source and binary forms, with or without |
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22 | | - modification, are permitted provided that the following conditions |
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23 | | - are met: |
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24 | | - |
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25 | | - * Redistributions of source code must retain the above copyright |
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26 | | - notice, this list of conditions and the following disclaimer. |
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27 | | - * Redistributions in binary form must reproduce the above copyright |
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28 | | - notice, this list of conditions and the following disclaimer in |
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29 | | - the documentation and/or other materials provided with the |
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30 | | - distribution. |
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31 | | - * Neither the name of Intel Corporation nor the names of its |
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32 | | - contributors may be used to endorse or promote products derived |
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33 | | - from this software without specific prior written permission. |
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34 | | - |
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35 | | - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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36 | | - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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37 | | - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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38 | | - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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39 | | - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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40 | | - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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41 | | - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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42 | | - DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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43 | | - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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44 | | - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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45 | | - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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46 | | -*/ |
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| 1 | +// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) |
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| 2 | +/* Copyright(c) 2014 - 2020 Intel Corporation */ |
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47 | 3 | #include <linux/delay.h> |
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48 | 4 | #include "adf_accel_devices.h" |
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49 | 5 | #include "adf_transport_internal.h" |
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.. | .. |
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51 | 7 | #include "adf_cfg.h" |
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52 | 8 | #include "adf_common_drv.h" |
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53 | 9 | |
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54 | | -static inline uint32_t adf_modulo(uint32_t data, uint32_t shift) |
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| 10 | +static inline u32 adf_modulo(u32 data, u32 shift) |
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55 | 11 | { |
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56 | | - uint32_t div = data >> shift; |
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57 | | - uint32_t mult = div << shift; |
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| 12 | + u32 div = data >> shift; |
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| 13 | + u32 mult = div << shift; |
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58 | 14 | |
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59 | 15 | return data - mult; |
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60 | 16 | } |
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61 | 17 | |
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62 | | -static inline int adf_check_ring_alignment(uint64_t addr, uint64_t size) |
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| 18 | +static inline int adf_check_ring_alignment(u64 addr, u64 size) |
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63 | 19 | { |
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64 | 20 | if (((size - 1) & addr) != 0) |
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65 | 21 | return -EFAULT; |
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66 | 22 | return 0; |
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67 | 23 | } |
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68 | 24 | |
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69 | | -static int adf_verify_ring_size(uint32_t msg_size, uint32_t msg_num) |
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| 25 | +static int adf_verify_ring_size(u32 msg_size, u32 msg_num) |
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70 | 26 | { |
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71 | 27 | int i = ADF_MIN_RING_SIZE; |
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72 | 28 | |
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.. | .. |
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77 | 33 | return ADF_DEFAULT_RING_SIZE; |
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78 | 34 | } |
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79 | 35 | |
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80 | | -static int adf_reserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) |
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| 36 | +static int adf_reserve_ring(struct adf_etr_bank_data *bank, u32 ring) |
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81 | 37 | { |
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82 | 38 | spin_lock(&bank->lock); |
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83 | 39 | if (bank->ring_mask & (1 << ring)) { |
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.. | .. |
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89 | 45 | return 0; |
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90 | 46 | } |
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91 | 47 | |
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92 | | -static void adf_unreserve_ring(struct adf_etr_bank_data *bank, uint32_t ring) |
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| 48 | +static void adf_unreserve_ring(struct adf_etr_bank_data *bank, u32 ring) |
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93 | 49 | { |
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94 | 50 | spin_lock(&bank->lock); |
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95 | 51 | bank->ring_mask &= ~(1 << ring); |
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96 | 52 | spin_unlock(&bank->lock); |
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97 | 53 | } |
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98 | 54 | |
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99 | | -static void adf_enable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring) |
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| 55 | +static void adf_enable_ring_irq(struct adf_etr_bank_data *bank, u32 ring) |
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100 | 56 | { |
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101 | 57 | spin_lock_bh(&bank->lock); |
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102 | 58 | bank->irq_mask |= (1 << ring); |
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.. | .. |
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106 | 62 | bank->irq_coalesc_timer); |
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107 | 63 | } |
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108 | 64 | |
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109 | | -static void adf_disable_ring_irq(struct adf_etr_bank_data *bank, uint32_t ring) |
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| 65 | +static void adf_disable_ring_irq(struct adf_etr_bank_data *bank, u32 ring) |
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110 | 66 | { |
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111 | 67 | spin_lock_bh(&bank->lock); |
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112 | 68 | bank->irq_mask &= ~(1 << ring); |
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.. | .. |
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114 | 70 | WRITE_CSR_INT_COL_EN(bank->csr_addr, bank->bank_number, bank->irq_mask); |
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115 | 71 | } |
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116 | 72 | |
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117 | | -int adf_send_message(struct adf_etr_ring_data *ring, uint32_t *msg) |
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| 73 | +int adf_send_message(struct adf_etr_ring_data *ring, u32 *msg) |
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118 | 74 | { |
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119 | 75 | if (atomic_add_return(1, ring->inflights) > |
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120 | 76 | ADF_MAX_INFLIGHTS(ring->ring_size, ring->msg_size)) { |
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.. | .. |
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136 | 92 | |
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137 | 93 | static int adf_handle_response(struct adf_etr_ring_data *ring) |
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138 | 94 | { |
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139 | | - uint32_t msg_counter = 0; |
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140 | | - uint32_t *msg = (uint32_t *)((uintptr_t)ring->base_addr + ring->head); |
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| 95 | + u32 msg_counter = 0; |
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| 96 | + u32 *msg = (u32 *)((uintptr_t)ring->base_addr + ring->head); |
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141 | 97 | |
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142 | 98 | while (*msg != ADF_RING_EMPTY_SIG) { |
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143 | | - ring->callback((uint32_t *)msg); |
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| 99 | + ring->callback((u32 *)msg); |
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144 | 100 | atomic_dec(ring->inflights); |
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145 | 101 | *msg = ADF_RING_EMPTY_SIG; |
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146 | 102 | ring->head = adf_modulo(ring->head + |
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147 | 103 | ADF_MSG_SIZE_TO_BYTES(ring->msg_size), |
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148 | 104 | ADF_RING_SIZE_MODULO(ring->ring_size)); |
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149 | 105 | msg_counter++; |
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150 | | - msg = (uint32_t *)((uintptr_t)ring->base_addr + ring->head); |
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| 106 | + msg = (u32 *)((uintptr_t)ring->base_addr + ring->head); |
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151 | 107 | } |
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152 | 108 | if (msg_counter > 0) |
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153 | 109 | WRITE_CSR_RING_HEAD(ring->bank->csr_addr, |
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.. | .. |
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158 | 114 | |
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159 | 115 | static void adf_configure_tx_ring(struct adf_etr_ring_data *ring) |
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160 | 116 | { |
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161 | | - uint32_t ring_config = BUILD_RING_CONFIG(ring->ring_size); |
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| 117 | + u32 ring_config = BUILD_RING_CONFIG(ring->ring_size); |
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162 | 118 | |
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163 | 119 | WRITE_CSR_RING_CONFIG(ring->bank->csr_addr, ring->bank->bank_number, |
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164 | 120 | ring->ring_number, ring_config); |
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.. | .. |
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166 | 122 | |
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167 | 123 | static void adf_configure_rx_ring(struct adf_etr_ring_data *ring) |
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168 | 124 | { |
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169 | | - uint32_t ring_config = |
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| 125 | + u32 ring_config = |
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170 | 126 | BUILD_RESP_RING_CONFIG(ring->ring_size, |
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171 | 127 | ADF_RING_NEAR_WATERMARK_512, |
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172 | 128 | ADF_RING_NEAR_WATERMARK_0); |
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.. | .. |
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180 | 136 | struct adf_etr_bank_data *bank = ring->bank; |
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181 | 137 | struct adf_accel_dev *accel_dev = bank->accel_dev; |
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182 | 138 | struct adf_hw_device_data *hw_data = accel_dev->hw_device; |
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183 | | - uint64_t ring_base; |
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184 | | - uint32_t ring_size_bytes = |
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| 139 | + u64 ring_base; |
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| 140 | + u32 ring_size_bytes = |
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185 | 141 | ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size); |
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186 | 142 | |
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187 | 143 | ring_size_bytes = ADF_RING_SIZE_BYTES_MIN(ring_size_bytes); |
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.. | .. |
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216 | 172 | |
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217 | 173 | static void adf_cleanup_ring(struct adf_etr_ring_data *ring) |
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218 | 174 | { |
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219 | | - uint32_t ring_size_bytes = |
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| 175 | + u32 ring_size_bytes = |
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220 | 176 | ADF_SIZE_TO_RING_SIZE_IN_BYTES(ring->ring_size); |
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221 | 177 | ring_size_bytes = ADF_RING_SIZE_BYTES_MIN(ring_size_bytes); |
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222 | 178 | |
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.. | .. |
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229 | 185 | } |
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230 | 186 | |
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231 | 187 | int adf_create_ring(struct adf_accel_dev *accel_dev, const char *section, |
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232 | | - uint32_t bank_num, uint32_t num_msgs, |
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233 | | - uint32_t msg_size, const char *ring_name, |
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| 188 | + u32 bank_num, u32 num_msgs, |
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| 189 | + u32 msg_size, const char *ring_name, |
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234 | 190 | adf_callback_fn callback, int poll_mode, |
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235 | 191 | struct adf_etr_ring_data **ring_ptr) |
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236 | 192 | { |
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.. | .. |
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238 | 194 | struct adf_etr_bank_data *bank; |
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239 | 195 | struct adf_etr_ring_data *ring; |
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240 | 196 | char val[ADF_CFG_MAX_VAL_LEN_IN_BYTES]; |
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241 | | - uint32_t ring_num; |
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| 197 | + u32 ring_num; |
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242 | 198 | int ret; |
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243 | 199 | |
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244 | 200 | if (bank_num >= GET_MAX_BANKS(accel_dev)) { |
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.. | .. |
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331 | 287 | |
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332 | 288 | static void adf_ring_response_handler(struct adf_etr_bank_data *bank) |
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333 | 289 | { |
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334 | | - uint32_t empty_rings, i; |
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| 290 | + u32 empty_rings, i; |
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335 | 291 | |
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336 | 292 | empty_rings = READ_CSR_E_STAT(bank->csr_addr, bank->bank_number); |
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337 | 293 | empty_rings = ~empty_rings & bank->irq_mask; |
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.. | .. |
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354 | 310 | |
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355 | 311 | static inline int adf_get_cfg_int(struct adf_accel_dev *accel_dev, |
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356 | 312 | const char *section, const char *format, |
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357 | | - uint32_t key, uint32_t *value) |
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| 313 | + u32 key, u32 *value) |
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358 | 314 | { |
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359 | 315 | char key_buf[ADF_CFG_MAX_KEY_LEN_IN_BYTES]; |
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360 | 316 | char val_buf[ADF_CFG_MAX_VAL_LEN_IN_BYTES]; |
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.. | .. |
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371 | 327 | |
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372 | 328 | static void adf_get_coalesc_timer(struct adf_etr_bank_data *bank, |
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373 | 329 | const char *section, |
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374 | | - uint32_t bank_num_in_accel) |
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| 330 | + u32 bank_num_in_accel) |
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375 | 331 | { |
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376 | 332 | if (adf_get_cfg_int(bank->accel_dev, section, |
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377 | 333 | ADF_ETRMGR_COALESCE_TIMER_FORMAT, |
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.. | .. |
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385 | 341 | |
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386 | 342 | static int adf_init_bank(struct adf_accel_dev *accel_dev, |
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387 | 343 | struct adf_etr_bank_data *bank, |
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388 | | - uint32_t bank_num, void __iomem *csr_addr) |
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| 344 | + u32 bank_num, void __iomem *csr_addr) |
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389 | 345 | { |
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390 | 346 | struct adf_hw_device_data *hw_data = accel_dev->hw_device; |
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391 | 347 | struct adf_etr_ring_data *ring; |
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392 | 348 | struct adf_etr_ring_data *tx_ring; |
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393 | | - uint32_t i, coalesc_enabled = 0; |
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| 349 | + u32 i, coalesc_enabled = 0; |
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394 | 350 | |
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395 | 351 | memset(bank, 0, sizeof(*bank)); |
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396 | 352 | bank->bank_number = bank_num; |
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.. | .. |
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462 | 418 | struct adf_etr_data *etr_data; |
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463 | 419 | struct adf_hw_device_data *hw_data = accel_dev->hw_device; |
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464 | 420 | void __iomem *csr_addr; |
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465 | | - uint32_t size; |
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466 | | - uint32_t num_banks = 0; |
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| 421 | + u32 size; |
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| 422 | + u32 num_banks = 0; |
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467 | 423 | int i, ret; |
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468 | 424 | |
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469 | 425 | etr_data = kzalloc_node(sizeof(*etr_data), GFP_KERNEL, |
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.. | .. |
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487 | 443 | /* accel_dev->debugfs_dir should always be non-NULL here */ |
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488 | 444 | etr_data->debug = debugfs_create_dir("transport", |
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489 | 445 | accel_dev->debugfs_dir); |
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490 | | - if (!etr_data->debug) { |
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491 | | - dev_err(&GET_DEV(accel_dev), |
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492 | | - "Unable to create transport debugfs entry\n"); |
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493 | | - ret = -ENOENT; |
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494 | | - goto err_bank_debug; |
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495 | | - } |
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496 | 446 | |
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497 | 447 | for (i = 0; i < num_banks; i++) { |
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498 | 448 | ret = adf_init_bank(accel_dev, &etr_data->banks[i], i, |
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.. | .. |
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505 | 455 | |
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506 | 456 | err_bank_all: |
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507 | 457 | debugfs_remove(etr_data->debug); |
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508 | | -err_bank_debug: |
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509 | 458 | kfree(etr_data->banks); |
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510 | 459 | err_bank: |
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511 | 460 | kfree(etr_data); |
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.. | .. |
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516 | 465 | |
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517 | 466 | static void cleanup_bank(struct adf_etr_bank_data *bank) |
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518 | 467 | { |
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519 | | - uint32_t i; |
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| 468 | + u32 i; |
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520 | 469 | |
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521 | 470 | for (i = 0; i < ADF_ETR_MAX_RINGS_PER_BANK; i++) { |
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522 | 471 | struct adf_accel_dev *accel_dev = bank->accel_dev; |
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.. | .. |
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536 | 485 | static void adf_cleanup_etr_handles(struct adf_accel_dev *accel_dev) |
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537 | 486 | { |
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538 | 487 | struct adf_etr_data *etr_data = accel_dev->transport; |
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539 | | - uint32_t i, num_banks = GET_MAX_BANKS(accel_dev); |
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| 488 | + u32 i, num_banks = GET_MAX_BANKS(accel_dev); |
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540 | 489 | |
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541 | 490 | for (i = 0; i < num_banks; i++) |
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542 | 491 | cleanup_bank(&etr_data->banks[i]); |
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