add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clocksource/timer-ti-32k.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /**
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  * timer-ti-32k.c - OMAP2 32k Timer Support
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  *
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@@ -20,21 +21,10 @@
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  * Roughly modelled after the OMAP1 MPU timer code.
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  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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  *
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- * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
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- *
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- * This program is free software: you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2  of
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- * the License as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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+ * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
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  */
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26
 
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+#include <linux/clk.h>
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 #include <linux/init.h>
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 #include <linux/time.h>
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 #include <linux/sched_clock.h>
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@@ -87,6 +77,49 @@
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 	return ti_32k_read_cycles(&ti_32k_timer.cs);
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 }
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+static void __init ti_32k_timer_enable_clock(struct device_node *np,
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+					     const char *name)
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+{
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+	struct clk *clock;
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+	int error;
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+
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+	clock = of_clk_get_by_name(np->parent, name);
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+	if (IS_ERR(clock)) {
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+		/* Only some SoCs have a separate interface clock */
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+		if (PTR_ERR(clock) == -EINVAL && !strncmp("ick", name, 3))
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+			return;
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+
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+		pr_warn("%s: could not get clock %s %li\n",
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+			__func__, name, PTR_ERR(clock));
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+		return;
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+	}
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+
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+	error = clk_prepare_enable(clock);
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+	if (error) {
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+		pr_warn("%s: could not enable %s: %i\n",
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+			__func__, name, error);
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+		return;
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+	}
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+}
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+
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+static void __init ti_32k_timer_module_init(struct device_node *np,
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+					    void __iomem *base)
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+{
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+	void __iomem *sysc = base + 4;
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+
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+	if (!of_device_is_compatible(np->parent, "ti,sysc"))
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+		return;
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+
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+	ti_32k_timer_enable_clock(np, "fck");
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+	ti_32k_timer_enable_clock(np, "ick");
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+
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+	/*
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+	 * Force idle module as wkup domain is active with MPU.
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+	 * No need to tag the module disabled for ti-sysc probe.
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+	 */
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+	writel_relaxed(0, sysc);
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+}
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+
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 static int __init ti_32k_timer_init(struct device_node *np)
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 {
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 	int ret;
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@@ -101,6 +134,7 @@
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 		ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
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135
 
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 	ti_32k_timer.counter = ti_32k_timer.base;
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+	ti_32k_timer_module_init(np, ti_32k_timer.base);
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138
 
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 	/*
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 	 * 32k sync Counter IP register offsets vary between the highlander
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@@ -115,6 +149,8 @@
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 	else
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 		ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
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+	pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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+
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 	ret = clocksource_register_hz(&ti_32k_timer.cs, 32768);
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 	if (ret) {
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 		pr_err("32k_counter: can't register clocksource\n");
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@@ -122,7 +158,6 @@
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 	}
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 	sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
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-	pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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 	return 0;
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 }