hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/clk/zynq/pll.c
....@@ -1,22 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Zynq PLL driver
34 *
45 * Copyright (C) 2013 Xilinx
56 *
67 * Sören Brinkmann <soren.brinkmann@xilinx.com>
7
- *
8
- * This program is free software: you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License v2 as published by
10
- * the Free Software Foundation.
11
- *
12
- * This program is distributed in the hope that it will be useful,
13
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
14
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15
- * GNU General Public License for more details.
16
- *
17
- * You should have received a copy of the GNU General Public License
18
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
19
- *
208 */
219 #include <linux/clk/zynq.h>
2210 #include <linux/clk-provider.h>
....@@ -90,7 +78,7 @@
9078 * makes probably sense to redundantly save fbdiv in the struct
9179 * zynq_pll to save the IO access.
9280 */
93
- fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
81
+ fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
9482 PLLCTRL_FBDIV_SHIFT;
9583
9684 return parent_rate * fbdiv;
....@@ -112,7 +100,7 @@
112100
113101 spin_lock_irqsave(clk->lock, flags);
114102
115
- reg = clk_readl(clk->pll_ctrl);
103
+ reg = readl(clk->pll_ctrl);
116104
117105 spin_unlock_irqrestore(clk->lock, flags);
118106
....@@ -138,10 +126,10 @@
138126 /* Power up PLL and wait for lock */
139127 spin_lock_irqsave(clk->lock, flags);
140128
141
- reg = clk_readl(clk->pll_ctrl);
129
+ reg = readl(clk->pll_ctrl);
142130 reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
143
- clk_writel(reg, clk->pll_ctrl);
144
- while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit)))
131
+ writel(reg, clk->pll_ctrl);
132
+ while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
145133 ;
146134
147135 spin_unlock_irqrestore(clk->lock, flags);
....@@ -168,9 +156,9 @@
168156 /* shut down PLL */
169157 spin_lock_irqsave(clk->lock, flags);
170158
171
- reg = clk_readl(clk->pll_ctrl);
159
+ reg = readl(clk->pll_ctrl);
172160 reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
173
- clk_writel(reg, clk->pll_ctrl);
161
+ writel(reg, clk->pll_ctrl);
174162
175163 spin_unlock_irqrestore(clk->lock, flags);
176164 }
....@@ -223,9 +211,9 @@
223211
224212 spin_lock_irqsave(pll->lock, flags);
225213
226
- reg = clk_readl(pll->pll_ctrl);
214
+ reg = readl(pll->pll_ctrl);
227215 reg &= ~PLLCTRL_BPQUAL_MASK;
228
- clk_writel(reg, pll->pll_ctrl);
216
+ writel(reg, pll->pll_ctrl);
229217
230218 spin_unlock_irqrestore(pll->lock, flags);
231219