hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/clk/tegra/clk-tegra-fixed.c
....@@ -1,17 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify it
5
- * under the terms and conditions of the GNU General Public License,
6
- * version 2, as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope it will be useful, but WITHOUT
9
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11
- * more details.
12
- *
13
- * You should have received a copy of the GNU General Public License
14
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
154 */
165
176 #include <linux/io.h>
....@@ -28,6 +17,10 @@
2817 #define OSC_CTRL 0x50
2918 #define OSC_CTRL_OSC_FREQ_SHIFT 28
3019 #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
20
+#define OSC_CTRL_MASK (0x3f2 | \
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+ (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
22
+
23
+static u32 osc_ctrl_ctx;
3124
3225 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
3326 unsigned long *input_freqs, unsigned int num,
....@@ -40,6 +33,7 @@
4033 unsigned osc_idx;
4134
4235 val = readl_relaxed(clk_base + OSC_CTRL);
36
+ osc_ctrl_ctx = val & OSC_CTRL_MASK;
4337 osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
4438
4539 if (osc_idx < num)
....@@ -52,7 +46,28 @@
5246 return -EINVAL;
5347 }
5448
49
+ dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
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+ if (!dt_clk)
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+ return 0;
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+
5553 osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
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+ *dt_clk = osc;
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+
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+ /* osc_div2 */
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+ dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
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+ if (dt_clk) {
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+ clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
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+ 0, 1, 2);
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+ *dt_clk = clk;
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+ }
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+
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+ /* osc_div4 */
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+ dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
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+ if (dt_clk) {
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+ clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
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+ 0, 1, 4);
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+ *dt_clk = clk;
70
+ }
5671
5772 dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
5873 if (!dt_clk)
....@@ -90,20 +105,14 @@
90105 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
91106 *dt_clk = clk;
92107 }
108
+}
93109
94
- /* clk_m_div2 */
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- dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
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- if (dt_clk) {
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- clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
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- CLK_SET_RATE_PARENT, 1, 2);
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- *dt_clk = clk;
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- }
110
+void tegra_clk_osc_resume(void __iomem *clk_base)
111
+{
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+ u32 val;
101113
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- /* clk_m_div4 */
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- dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
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- if (dt_clk) {
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- clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
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- CLK_SET_RATE_PARENT, 1, 4);
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- *dt_clk = clk;
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- }
114
+ val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
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+ val |= osc_ctrl_ctx;
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+ writel_relaxed(val, clk_base + OSC_CTRL);
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+ fence_udelay(2, clk_base);
109118 }