add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clk/tegra/clk-tegra-fixed.c
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..
@@ -1,17 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2012, 2013, NVIDIA CORPORATION.  All rights reserved.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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  */
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5
 
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 #include <linux/io.h>
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..
@@ -28,6 +17,10 @@
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 #define OSC_CTRL			0x50
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 #define OSC_CTRL_OSC_FREQ_SHIFT		28
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 #define OSC_CTRL_PLL_REF_DIV_SHIFT	26
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+#define OSC_CTRL_MASK			(0x3f2 |	\
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+					(0xf << OSC_CTRL_OSC_FREQ_SHIFT))
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+
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+static u32 osc_ctrl_ctx;
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24
 
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 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
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 			      unsigned long *input_freqs, unsigned int num,
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@@ -40,6 +33,7 @@
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 	unsigned osc_idx;
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34
 
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 	val = readl_relaxed(clk_base + OSC_CTRL);
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+	osc_ctrl_ctx = val & OSC_CTRL_MASK;
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 	osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
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38
 
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 	if (osc_idx < num)
..
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@@ -52,7 +46,28 @@
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 		return -EINVAL;
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 	}
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48
 
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+	dt_clk = tegra_lookup_dt_id(tegra_clk_osc, clks);
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+	if (!dt_clk)
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+		return 0;
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+
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 	osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq);
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+	*dt_clk = osc;
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+
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+	/* osc_div2 */
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+	dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks);
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+	if (dt_clk) {
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+		clk = clk_register_fixed_factor(NULL, "osc_div2", "osc",
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+						0, 1, 2);
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+		*dt_clk = clk;
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+	}
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+
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+	/* osc_div4 */
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+	dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks);
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+	if (dt_clk) {
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+		clk = clk_register_fixed_factor(NULL, "osc_div4", "osc",
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+						0, 1, 4);
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+		*dt_clk = clk;
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+	}
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 	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
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 	if (!dt_clk)
..
..
@@ -90,20 +105,14 @@
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 		clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, 0, 32768);
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 		*dt_clk = clk;
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 	}
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+}
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-	/* clk_m_div2 */
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-	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
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-	if (dt_clk) {
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-		clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
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-					CLK_SET_RATE_PARENT, 1, 2);
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-		*dt_clk = clk;
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-	}
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+void tegra_clk_osc_resume(void __iomem *clk_base)
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+{
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+	u32 val;
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-	/* clk_m_div4 */
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-	dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
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-	if (dt_clk) {
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-		clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
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-					CLK_SET_RATE_PARENT, 1, 4);
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-		*dt_clk = clk;
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-	}
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+	val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
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+	val |= osc_ctrl_ctx;
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+	writel_relaxed(val, clk_base + OSC_CTRL);
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+	fence_udelay(2, clk_base);
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 }