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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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1 | 2 | /* |
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2 | 3 | * Copyright 2011-2012 Calxeda, Inc. |
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3 | 4 | * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> |
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4 | 5 | * |
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5 | | - * This program is free software; you can redistribute it and/or modify |
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6 | | - * it under the terms of the GNU General Public License as published by |
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7 | | - * the Free Software Foundation; either version 2 of the License, or |
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8 | | - * (at your option) any later version. |
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9 | | - * |
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10 | | - * This program is distributed in the hope that it will be useful, |
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11 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | | - * GNU General Public License for more details. |
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14 | | - * |
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15 | 6 | * Based from clk-highbank.c |
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16 | | - * |
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17 | 7 | */ |
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18 | 8 | #include <linux/slab.h> |
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19 | 9 | #include <linux/clk-provider.h> |
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.. | .. |
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65 | 55 | struct socfpga_periph_clk *periph_clk; |
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66 | 56 | const char *clk_name = node->name; |
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67 | 57 | const char *parent_name[SOCFPGA_MAX_PARENTS]; |
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68 | | - struct clk_init_data init = {}; |
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| 58 | + struct clk_init_data init; |
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69 | 59 | int rc; |
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70 | 60 | u32 fixed_div; |
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71 | 61 | u32 div_reg[3]; |
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