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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/clk/samsung/clk-exynos5433.c
....@@ -1,10 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
34  * Author: Chanwoo Choi <cw00.choi@samsung.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
85  *
96  * Common Clock Framework support for Exynos5433 SoC.
107  */
....@@ -176,6 +173,17 @@
176173 	ENABLE_IP_TOP,
177174 	ENABLE_CMU_TOP,
178175 	ENABLE_CMU_TOP_DIV_STAT,
176
+};
177
+
178
+static const struct samsung_clk_reg_dump top_suspend_regs[] = {
179
+	/* force all aclk clocks enabled */
180
+	{ ENABLE_ACLK_TOP, 0x67ecffed },
181
+	/* force all sclk_uart clocks enabled */
182
+	{ ENABLE_SCLK_TOP_PERIC, 0x38 },
183
+	/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
184
+	{ ISP_PLL_CON0, 0x85cc0502 },
185
+	/* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
186
+	{ AUD_PLL_CON0, 0x84830202 },
179187 };
180188 
181189 /* list of all parent clock list */
....@@ -549,7 +557,7 @@
549557 	/* ENABLE_ACLK_TOP */
550558 	GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
551559 			ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
552
-	GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
560
+	GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
553561 			"div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
554562 			29, CLK_IGNORE_UNUSED, 0),
555563 	GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
....@@ -558,10 +566,10 @@
558566 	GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
559567 			ENABLE_ACLK_TOP, 25,
560568 			CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
561
-	GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
569
+	GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
562570 			ENABLE_ACLK_TOP, 24,
563571 			CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
564
-	GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
572
+	GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
565573 			ENABLE_ACLK_TOP, 23,
566574 			CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
567575 	GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
....@@ -793,6 +801,8 @@
793801 	.nr_clk_ids		= TOP_NR_CLK,
794802 	.clk_regs		= top_clk_regs,
795803 	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
804
+	.suspend_regs		= top_suspend_regs,
805
+	.nr_suspend_regs	= ARRAY_SIZE(top_suspend_regs),
796806 };
797807 
798808 static void __init exynos5433_cmu_top_init(struct device_node *np)
....@@ -821,6 +831,13 @@
821831 	MUX_SEL_CPIF0,
822832 	DIV_CPIF,
823833 	ENABLE_SCLK_CPIF,
834
+};
835
+
836
+static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
837
+	/* force all sclk clocks enabled */
838
+	{ ENABLE_SCLK_CPIF, 0x3ff },
839
+	/* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
840
+	{ MPHY_PLL_CON0, 0x81c70601 },
824841 };
825842 
826843 /* list of all parent clock list */
....@@ -863,6 +880,8 @@
863880 	.nr_clk_ids		= CPIF_NR_CLK,
864881 	.clk_regs		= cpif_clk_regs,
865882 	.nr_clk_regs		= ARRAY_SIZE(cpif_clk_regs),
883
+	.suspend_regs		= cpif_suspend_regs,
884
+	.nr_suspend_regs	= ARRAY_SIZE(cpif_suspend_regs),
866885 };
867886 
868887 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
....@@ -1548,6 +1567,13 @@
15481567 	ENABLE_IP_PERIC2,
15491568 };
15501569 
1570
+static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
1571
+	/* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
1572
+	{ ENABLE_PCLK_PERIC0, 0xe00ff000 },
1573
+	/* sclk: uart2-0 */
1574
+	{ ENABLE_SCLK_PERIC, 0x7 },
1575
+};
1576
+
15511577 static const struct samsung_div_clock peric_div_clks[] __initconst = {
15521578 	/* DIV_PERIC */
15531579 	DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
....@@ -1707,6 +1733,8 @@
17071733 	.nr_clk_ids		= PERIC_NR_CLK,
17081734 	.clk_regs		= peric_clk_regs,
17091735 	.nr_clk_regs		= ARRAY_SIZE(peric_clk_regs),
1736
+	.suspend_regs		= peric_suspend_regs,
1737
+	.nr_suspend_regs	= ARRAY_SIZE(peric_suspend_regs),
17101738 };
17111739 
17121740 static void __init exynos5433_cmu_peric_init(struct device_node *np)
....@@ -3651,6 +3679,7 @@
36513679 {
36523680 	void __iomem *reg_base;
36533681 	struct samsung_clk_provider *ctx;
3682
+	struct clk_hw **hws;
36543683 
36553684 	reg_base = of_iomap(np, 0);
36563685 	if (!reg_base) {
....@@ -3673,8 +3702,10 @@
36733702 	samsung_clk_register_gate(ctx, apollo_gate_clks,
36743703 				  ARRAY_SIZE(apollo_gate_clks));
36753704 
3705
+	hws = ctx->clk_data.hws;
3706
+
36763707 	exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
3677
-		mout_apollo_p[0], mout_apollo_p[1], 0x200,
3708
+		hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200,
36783709 		exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
36793710 		CLK_CPU_HAS_E5433_REGS_LAYOUT);
36803711 
....@@ -3905,6 +3936,7 @@
39053936 {
39063937 	void __iomem *reg_base;
39073938 	struct samsung_clk_provider *ctx;
3939
+	struct clk_hw **hws;
39083940 
39093941 	reg_base = of_iomap(np, 0);
39103942 	if (!reg_base) {
....@@ -3927,8 +3959,10 @@
39273959 	samsung_clk_register_gate(ctx, atlas_gate_clks,
39283960 				  ARRAY_SIZE(atlas_gate_clks));
39293961 
3962
+	hws = ctx->clk_data.hws;
3963
+
39303964 	exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
3931
-		mout_atlas_p[0], mout_atlas_p[1], 0x200,
3965
+		hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200,
39323966 		exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
39333967 		CLK_CPU_HAS_E5433_REGS_LAYOUT);
39343968 
....@@ -5438,6 +5472,35 @@
54385472 	.clk_name		= "aclk_cam1_400",
54395473 };
54405474 
5475
+/*
5476
+ * Register offset definitions for CMU_IMEM
5477
+ */
5478
+#define ENABLE_ACLK_IMEM_SLIMSSS		0x080c
5479
+#define ENABLE_PCLK_IMEM_SLIMSSS		0x0908
5480
+
5481
+static const unsigned long imem_clk_regs[] __initconst = {
5482
+	ENABLE_ACLK_IMEM_SLIMSSS,
5483
+	ENABLE_PCLK_IMEM_SLIMSSS,
5484
+};
5485
+
5486
+static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
5487
+	/* ENABLE_ACLK_IMEM_SLIMSSS */
5488
+	GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",
5489
+			ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5490
+
5491
+	/* ENABLE_PCLK_IMEM_SLIMSSS */
5492
+	GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",
5493
+			ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
5494
+};
5495
+
5496
+static const struct samsung_cmu_info imem_cmu_info __initconst = {
5497
+	.gate_clks		= imem_gate_clks,
5498
+	.nr_gate_clks		= ARRAY_SIZE(imem_gate_clks),
5499
+	.nr_clk_ids		= IMEM_NR_CLK,
5500
+	.clk_regs		= imem_clk_regs,
5501
+	.nr_clk_regs		= ARRAY_SIZE(imem_clk_regs),
5502
+	.clk_name		= "aclk_imem_200",
5503
+};
54415504 
54425505 struct exynos5433_cmu_data {
54435506 	struct samsung_clk_reg_dump *clk_save;
....@@ -5534,8 +5597,8 @@
55345597 	data->nr_clk_save = info->nr_clk_regs;
55355598 	data->clk_suspend = info->suspend_regs;
55365599 	data->nr_clk_suspend = info->nr_suspend_regs;
5537
-	data->nr_pclks = of_count_phandle_with_args(dev->of_node, "clocks",
5538
-						    "#clock-cells");
5600
+	data->nr_pclks = of_clk_get_parent_count(dev->of_node);
5601
+
55395602 	if (data->nr_pclks > 0) {
55405603 		data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
55415604 					   data->nr_pclks, GFP_KERNEL);
....@@ -5635,6 +5698,9 @@
56355698 		.compatible = "samsung,exynos5433-cmu-mscl",
56365699 		.data = &mscl_cmu_info,
56375700 	}, {
5701
+		.compatible = "samsung,exynos5433-cmu-imem",
5702
+		.data = &imem_cmu_info,
5703
+	}, {
56385704 	},
56395705 };
56405706