add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clk/samsung/clk-exynos3250.c
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@@ -1,18 +1,15 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  *
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  * Common Clock Framework support for Exynos3250 SoC.
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  */
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 #include <linux/clk-provider.h>
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+#include <linux/io.h>
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 #include <linux/of.h>
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 #include <linux/of_address.h>
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 #include <linux/platform_device.h>
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-#include <linux/syscore_ops.h>
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 #include <dt-bindings/clock/exynos3250.h>
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@@ -811,14 +808,16 @@
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 static void __init exynos3250_cmu_init(struct device_node *np)
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 {
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 	struct samsung_clk_provider *ctx;
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+	struct clk_hw **hws;
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 	ctx = samsung_cmu_register_one(np, &cmu_info);
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 	if (!ctx)
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 		return;
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+	hws = ctx->clk_data.hws;
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 	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
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-			mout_core_p[0], mout_core_p[1], 0x14200,
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-			e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
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+			hws[CLK_MOUT_APLL], hws[CLK_MOUT_MPLL_USER_C],
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+			0x14200, e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d),
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 			CLK_CPU_HAS_DIV1);
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 	exynos3_core_down_clock(ctx->reg_base);