forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/clk/rockchip/clk-rk3528.c
....@@ -136,7 +136,6 @@
136136 
137137 PNAME(mux_pll_p)                        = { "xin24m" };
138138 PNAME(mux_24m_32k_p)                    = { "xin24m", "clk_32k" };
139
-PNAME(mux_apll_gpll_p)                  = { "apll", "gpll" };
140139 PNAME(mux_gpll_cpll_p)                  = { "gpll", "cpll" };
141140 PNAME(mux_gpll_cpll_xin24m_p)           = { "gpll", "cpll", "xin24m" };
142141 PNAME(mux_100m_50m_24m_p)               = { "clk_100m_src", "clk_50m_src", "xin24m" };
....@@ -197,8 +196,6 @@
197196 #define MFLAGS CLK_MUX_HIWORD_MASK
198197 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
199198 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
200
-
201
-#define RK3528_FRAC_MAX_PRATE		1188000000
202199 
203200 static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata =
204201 	MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
....@@ -304,7 +301,7 @@
304301 	                RK3528_CLKGATE_CON(0), 12, GFLAGS),
305302 	COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
306303 	                  RK3528_CLKSEL_CON(5), 0,
307
-	                  RK3528_CLKGATE_CON(0), 13, GFLAGS, &rk3528_uart0_fracmux, RK3528_FRAC_MAX_PRATE),
304
+	                  RK3528_CLKGATE_CON(0), 13, GFLAGS, &rk3528_uart0_fracmux),
308305 	GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
309306 	     RK3528_CLKGATE_CON(0), 14, GFLAGS),
310307 
....@@ -313,7 +310,7 @@
313310 	                RK3528_CLKGATE_CON(0), 15, GFLAGS),
314311 	COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
315312 	                  RK3528_CLKSEL_CON(7), 0,
316
-	                  RK3528_CLKGATE_CON(1), 0, GFLAGS, &rk3528_uart1_fracmux, RK3528_FRAC_MAX_PRATE),
313
+	                  RK3528_CLKGATE_CON(1), 0, GFLAGS, &rk3528_uart1_fracmux),
317314 	GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
318315 	     RK3528_CLKGATE_CON(1), 1, GFLAGS),
319316 
....@@ -322,7 +319,7 @@
322319 	                RK3528_CLKGATE_CON(1), 2, GFLAGS),
323320 	COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
324321 	                  RK3528_CLKSEL_CON(9), 0,
325
-	                  RK3528_CLKGATE_CON(1), 3, GFLAGS, &rk3528_uart2_fracmux, RK3528_FRAC_MAX_PRATE),
322
+	                  RK3528_CLKGATE_CON(1), 3, GFLAGS, &rk3528_uart2_fracmux),
326323 	GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
327324 	     RK3528_CLKGATE_CON(1), 4, GFLAGS),
328325 
....@@ -331,7 +328,7 @@
331328 	                RK3528_CLKGATE_CON(1), 5, GFLAGS),
332329 	COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
333330 	                  RK3528_CLKSEL_CON(11), 0,
334
-	                  RK3528_CLKGATE_CON(1), 6, GFLAGS, &rk3528_uart3_fracmux, RK3528_FRAC_MAX_PRATE),
331
+	                  RK3528_CLKGATE_CON(1), 6, GFLAGS, &rk3528_uart3_fracmux),
335332 	GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
336333 	     RK3528_CLKGATE_CON(1), 7, GFLAGS),
337334 
....@@ -340,7 +337,7 @@
340337 	                RK3528_CLKGATE_CON(1), 8, GFLAGS),
341338 	COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
342339 	                  RK3528_CLKSEL_CON(13), 0,
343
-	                  RK3528_CLKGATE_CON(1), 9, GFLAGS, &rk3528_uart4_fracmux, RK3528_FRAC_MAX_PRATE),
340
+	                  RK3528_CLKGATE_CON(1), 9, GFLAGS, &rk3528_uart4_fracmux),
344341 	GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
345342 	     RK3528_CLKGATE_CON(1), 10, GFLAGS),
346343 
....@@ -349,7 +346,7 @@
349346 	                RK3528_CLKGATE_CON(1), 11, GFLAGS),
350347 	COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
351348 	                  RK3528_CLKSEL_CON(15), 0,
352
-	                  RK3528_CLKGATE_CON(1), 12, GFLAGS, &rk3528_uart5_fracmux, RK3528_FRAC_MAX_PRATE),
349
+	                  RK3528_CLKGATE_CON(1), 12, GFLAGS, &rk3528_uart5_fracmux),
353350 	GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
354351 	     RK3528_CLKGATE_CON(1), 13, GFLAGS),
355352 
....@@ -358,7 +355,7 @@
358355 	                RK3528_CLKGATE_CON(1), 14, GFLAGS),
359356 	COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
360357 	                  RK3528_CLKSEL_CON(17), 0,
361
-	                  RK3528_CLKGATE_CON(1), 15, GFLAGS, &rk3528_uart6_fracmux, RK3528_FRAC_MAX_PRATE),
358
+	                  RK3528_CLKGATE_CON(1), 15, GFLAGS, &rk3528_uart6_fracmux),
362359 	GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
363360 	     RK3528_CLKGATE_CON(2), 0, GFLAGS),
364361 
....@@ -367,7 +364,7 @@
367364 	                RK3528_CLKGATE_CON(2), 1, GFLAGS),
368365 	COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
369366 	                  RK3528_CLKSEL_CON(19), 0,
370
-	                  RK3528_CLKGATE_CON(2), 2, GFLAGS, &rk3528_uart7_fracmux, RK3528_FRAC_MAX_PRATE),
367
+	                  RK3528_CLKGATE_CON(2), 2, GFLAGS, &rk3528_uart7_fracmux),
371368 	GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
372369 	     RK3528_CLKGATE_CON(2), 3, GFLAGS),
373370 
....@@ -376,7 +373,7 @@
376373 	                RK3528_CLKGATE_CON(2), 5, GFLAGS),
377374 	COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
378375 	                  RK3528_CLKSEL_CON(21), 0,
379
-	                  RK3528_CLKGATE_CON(2), 6, GFLAGS, &mclk_i2s0_2ch_sai_src_fracmux, RK3528_FRAC_MAX_PRATE),
376
+	                  RK3528_CLKGATE_CON(2), 6, GFLAGS, &mclk_i2s0_2ch_sai_src_fracmux),
380377 	GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0,
381378 	     RK3528_CLKGATE_CON(2), 7, GFLAGS),
382379 
....@@ -385,7 +382,7 @@
385382 	                RK3528_CLKGATE_CON(2), 11, GFLAGS),
386383 	COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT,
387384 	                  RK3528_CLKSEL_CON(25), 0,
388
-	                  RK3528_CLKGATE_CON(2), 12, GFLAGS, &mclk_i2s1_8ch_sai_src_fracmux, RK3528_FRAC_MAX_PRATE),
385
+	                  RK3528_CLKGATE_CON(2), 12, GFLAGS, &mclk_i2s1_8ch_sai_src_fracmux),
389386 	GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0,
390387 	     RK3528_CLKGATE_CON(2), 13, GFLAGS),
391388 
....@@ -394,7 +391,7 @@
394391 	                RK3528_CLKGATE_CON(2), 14, GFLAGS),
395392 	COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
396393 	                  RK3528_CLKSEL_CON(27), 0,
397
-	                  RK3528_CLKGATE_CON(2), 15, GFLAGS, &mclk_i2s2_2ch_sai_src_fracmux, RK3528_FRAC_MAX_PRATE),
394
+	                  RK3528_CLKGATE_CON(2), 15, GFLAGS, &mclk_i2s2_2ch_sai_src_fracmux),
398395 	GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0,
399396 	     RK3528_CLKGATE_CON(3), 0, GFLAGS),
400397 
....@@ -403,7 +400,7 @@
403400 	                RK3528_CLKGATE_CON(2), 8, GFLAGS),
404401 	COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT,
405402 	                  RK3528_CLKSEL_CON(23), 0,
406
-	                  RK3528_CLKGATE_CON(2), 9, GFLAGS, &mclk_i2s3_8ch_sai_src_fracmux, RK3528_FRAC_MAX_PRATE),
403
+	                  RK3528_CLKGATE_CON(2), 9, GFLAGS, &mclk_i2s3_8ch_sai_src_fracmux),
407404 	GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0,
408405 	     RK3528_CLKGATE_CON(2), 10, GFLAGS),
409406 
....@@ -412,7 +409,7 @@
412409 	                RK3528_CLKGATE_CON(3), 4, GFLAGS),
413410 	COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT,
414411 	                  RK3528_CLKSEL_CON(31), 0,
415
-	                  RK3528_CLKGATE_CON(3), 5, GFLAGS, &mclk_spdif_src_fracmux, RK3528_FRAC_MAX_PRATE),
412
+	                  RK3528_CLKGATE_CON(3), 5, GFLAGS, &mclk_spdif_src_fracmux),
416413 	GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0,
417414 	     RK3528_CLKGATE_CON(3), 6, GFLAGS),
418415 
....@@ -550,7 +547,7 @@
550547 
551548 	COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0,
552549 	               RK3528_PMU_CLKSEL_CON(1), 0,
553
-	               RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS, 0),
550
+	               RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS),
554551 	/* clk_32k: internal! No path from external osc 32k */
555552 	MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL,
556553 	    RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS),
....@@ -803,12 +800,12 @@
803800 	COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
804801 	                RK3528_CLKSEL_CON(83), 0, 2, MFLAGS,
805802 	                RK3528_CLKGATE_CON(39), 0, GFLAGS),
806
-	GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
807
-	     RK3528_CLKGATE_CON(39), 8, GFLAGS | CLK_GATE_NO_SET_RATE),
808
-	GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0,
809
-	     RK3528_CLKGATE_CON(39), 11, GFLAGS | CLK_GATE_NO_SET_RATE),
810
-	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0,
811
-	     RK3528_CLKGATE_CON(41), 0, GFLAGS | CLK_GATE_NO_SET_RATE),
803
+	GATE_NO_SET_RATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
804
+	                 RK3528_CLKGATE_CON(39), 8, GFLAGS),
805
+	GATE_NO_SET_RATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0,
806
+	                 RK3528_CLKGATE_CON(39), 11, GFLAGS),
807
+	GATE_NO_SET_RATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0,
808
+	                 RK3528_CLKGATE_CON(41), 0, GFLAGS),
812809 
813810 	COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0,
814811 	          RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS,
....@@ -938,15 +935,15 @@
938935 	COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
939936 	                RK3528_CLKSEL_CON(60), 0, 2, MFLAGS,
940937 	                RK3528_CLKGATE_CON(25), 0, GFLAGS),
941
-	GATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0,
942
-	     RK3528_CLKGATE_CON(26), 1, GFLAGS | CLK_GATE_NO_SET_RATE),
943
-	GATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0,
944
-	     RK3528_CLKGATE_CON(28), 5, GFLAGS | CLK_GATE_NO_SET_RATE),
945
-	GATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0,
946
-	     RK3528_CLKGATE_CON(30), 3, GFLAGS | CLK_GATE_NO_SET_RATE),
938
+	GATE_NO_SET_RATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0,
939
+	                 RK3528_CLKGATE_CON(26), 1, GFLAGS),
940
+	GATE_NO_SET_RATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0,
941
+	                 RK3528_CLKGATE_CON(28), 5, GFLAGS),
942
+	GATE_NO_SET_RATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0,
943
+	                 RK3528_CLKGATE_CON(30), 3, GFLAGS),
947944 
948
-	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0,
949
-	     RK3528_CLKGATE_CON(33), 1, GFLAGS | CLK_GATE_NO_SET_RATE),
945
+	GATE_NO_SET_RATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0,
946
+	                 RK3528_CLKGATE_CON(33), 1, GFLAGS),
950947 
951948 	COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
952949 	                RK3528_CLKSEL_CON(61), 2, 2, MFLAGS,
....@@ -996,7 +993,7 @@
996993 	                RK3528_CLKSEL_CON(61), 0, 2, MFLAGS,
997994 	                RK3528_CLKGATE_CON(25), 3, GFLAGS),
998995 	GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0,
999
-	     RK3528_CLKGATE_CON(25), 9, GFLAGS | CLK_GATE_NO_SET_RATE),
996
+	     RK3528_CLKGATE_CON(25), 9, GFLAGS),
1000997 
1001998 	COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
1002999 	                RK3528_CLKSEL_CON(63), 10, 2, MFLAGS,
....@@ -1108,6 +1105,7 @@
11081105 {
11091106 	struct rockchip_clk_provider *ctx;
11101107 	void __iomem *reg_base;
1108
+	struct clk **clks;
11111109 
11121110 	reg_base = of_iomap(np, 0);
11131111 	if (!reg_base) {
....@@ -1123,13 +1121,14 @@
11231121 		iounmap(reg_base);
11241122 		return;
11251123 	}
1124
+	clks = ctx->clk_data.clks;
11261125 
11271126 	rockchip_clk_register_plls(ctx, rk3528_pll_clks,
11281127 				   ARRAY_SIZE(rk3528_pll_clks),
11291128 				   RK3528_GRF_SOC_STATUS0);
11301129 
11311130 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1132
-				     mux_apll_gpll_p, ARRAY_SIZE(mux_apll_gpll_p),
1131
+				     2, clks[PLL_APLL], clks[PLL_GPLL],
11331132 				     &rk3528_cpuclk_data, rk3528_cpuclk_rates,
11341133 				     ARRAY_SIZE(rk3528_cpuclk_rates));
11351134 	rockchip_clk_register_branches(ctx, rk3528_clk_branches,