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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/clk/rockchip/clk-rk3328.c
....@@ -1,21 +1,15 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
34  * Author: Elaine <zhangqing@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
145  */
156 
167 #include <linux/clk-provider.h>
8
+#include <linux/io.h>
9
+#include <linux/module.h>
1710 #include <linux/of.h>
1811 #include <linux/of_address.h>
12
+#include <linux/of_device.h>
1913 #include <linux/syscore_ops.h>
2014 #include <dt-bindings/clock/rk3328-cru.h>
2115 #include "clk.h"
....@@ -24,9 +18,6 @@
2418 #define RK3328_GRF_SOC_STATUS0		0x480
2519 #define RK3328_GRF_MAC_CON1		0x904
2620 #define RK3328_GRF_MAC_CON2		0x908
27
-#define RK3328_I2S_FRAC_MAX_PRATE       600000000
28
-#define RK3328_UART_FRAC_MAX_PRATE	600000000
29
-#define RK3328_SPDIF_FRAC_MAX_PRATE	600000000
3021 
3122 enum rk3328_plls {
3223 	apll, dpll, cpll, gpll, npll,
....@@ -152,7 +143,7 @@
152143 };
153144 
154145 PNAME(mux_pll_p)		= { "xin24m" };
155
-PNAME(mux_hdmiphy_gpll_p)	= { "hdmiphy", "gpll" };
146
+
156147 PNAME(mux_2plls_p)		= { "cpll", "gpll" };
157148 PNAME(mux_gpll_cpll_p)		= { "gpll", "cpll" };
158149 PNAME(mux_cpll_gpll_apll_p)	= { "cpll", "gpll", "apll" };
....@@ -302,18 +293,18 @@
302293 			RK3328_CLKGATE_CON(0), 1, GFLAGS),
303294 	GATE(0, "npll_core", "npll", CLK_IGNORE_UNUSED,
304295 			RK3328_CLKGATE_CON(0), 12, GFLAGS),
305
-	COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
296
+	COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
306297 			RK3328_CLKSEL_CON(1), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
307298 			RK3328_CLKGATE_CON(7), 0, GFLAGS),
308
-	COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
299
+	COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IS_CRITICAL,
309300 			RK3328_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
310301 			RK3328_CLKGATE_CON(7), 1, GFLAGS),
311
-	GATE(0, "aclk_core_niu", "aclk_core", 0,
302
+	GATE(0, "aclk_core_niu", "aclk_core", CLK_IS_CRITICAL,
312303 			RK3328_CLKGATE_CON(13), 0, GFLAGS),
313
-	GATE(0, "aclk_gic400", "aclk_core", CLK_IGNORE_UNUSED,
304
+	GATE(0, "aclk_gic400", "aclk_core", CLK_IS_CRITICAL,
314305 			RK3328_CLKGATE_CON(13), 1, GFLAGS),
315306 
316
-	GATE(0, "clk_jtag", "jtag_clkin", CLK_IGNORE_UNUSED,
307
+	GATE(0, "clk_jtag", "jtag_clkin", CLK_IS_CRITICAL,
317308 			RK3328_CLKGATE_CON(7), 2, GFLAGS),
318309 
319310 	/* PD_GPU */
....@@ -322,35 +313,34 @@
322313 			RK3328_CLKGATE_CON(6), 6, GFLAGS),
323314 	GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", CLK_SET_RATE_PARENT,
324315 			RK3328_CLKGATE_CON(14), 0, GFLAGS),
325
-	GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", 0,
316
+	GATE(0, "aclk_gpu_niu", "aclk_gpu_pre", CLK_IS_CRITICAL,
326317 			RK3328_CLKGATE_CON(14), 1, GFLAGS),
327318 
328319 	/* PD_DDR */
329
-	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
330
-			 RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
331
-			 ROCKCHIP_DDRCLK_SIP_V2),
332
-
333
-	GATE(0, "clk_ddrmsch", "sclk_ddrc", CLK_IGNORE_UNUSED,
320
+	COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IS_CRITICAL,
321
+			RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
322
+			RK3328_CLKGATE_CON(0), 4, GFLAGS),
323
+	GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IS_CRITICAL,
334324 			RK3328_CLKGATE_CON(18), 6, GFLAGS),
335
-	GATE(0, "clk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED,
325
+	GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IS_CRITICAL,
336326 			RK3328_CLKGATE_CON(18), 5, GFLAGS),
337
-	GATE(0, "aclk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED,
327
+	GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
338328 			RK3328_CLKGATE_CON(18), 4, GFLAGS),
339329 	GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
340330 			RK3328_CLKGATE_CON(0), 6, GFLAGS),
341331 
342
-	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, 0,
332
+	COMPOSITE(PCLK_DDR, "pclk_ddr", mux_2plls_hdmiphy_p, CLK_IS_CRITICAL,
343333 			RK3328_CLKSEL_CON(4), 13, 2, MFLAGS, 8, 3, DFLAGS,
344334 			RK3328_CLKGATE_CON(7), 4, GFLAGS),
345
-	GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IGNORE_UNUSED,
335
+	GATE(0, "pclk_ddrupctl", "pclk_ddr", CLK_IS_CRITICAL,
346336 			RK3328_CLKGATE_CON(18), 1, GFLAGS),
347
-	GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IGNORE_UNUSED,
337
+	GATE(0, "pclk_ddr_msch", "pclk_ddr", CLK_IS_CRITICAL,
348338 			RK3328_CLKGATE_CON(18), 2, GFLAGS),
349
-	GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IGNORE_UNUSED,
339
+	GATE(0, "pclk_ddr_mon", "pclk_ddr", CLK_IS_CRITICAL,
350340 			RK3328_CLKGATE_CON(18), 3, GFLAGS),
351341 	GATE(0, "pclk_ddrstdby", "pclk_ddr", CLK_IGNORE_UNUSED,
352342 			RK3328_CLKGATE_CON(18), 7, GFLAGS),
353
-	GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
343
+	GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IS_CRITICAL,
354344 			RK3328_CLKGATE_CON(18), 9, GFLAGS),
355345 
356346 	/*
....@@ -358,18 +348,18 @@
358348 	 */
359349 
360350 	/* PD_BUS */
361
-	COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, 0,
351
+	COMPOSITE(ACLK_BUS_PRE, "aclk_bus_pre", mux_2plls_hdmiphy_p, CLK_IS_CRITICAL,
362352 			RK3328_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS,
363353 			RK3328_CLKGATE_CON(8), 0, GFLAGS),
364
-	COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", 0,
354
+	COMPOSITE_NOMUX(HCLK_BUS_PRE, "hclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
365355 			RK3328_CLKSEL_CON(1), 8, 2, DFLAGS,
366356 			RK3328_CLKGATE_CON(8), 1, GFLAGS),
367
-	COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", 0,
357
+	COMPOSITE_NOMUX(PCLK_BUS_PRE, "pclk_bus_pre", "aclk_bus_pre", CLK_IS_CRITICAL,
368358 			RK3328_CLKSEL_CON(1), 12, 3, DFLAGS,
369359 			RK3328_CLKGATE_CON(8), 2, GFLAGS),
370
-	GATE(0, "pclk_bus", "pclk_bus_pre", 0,
360
+	GATE(0, "pclk_bus", "pclk_bus_pre", CLK_IS_CRITICAL,
371361 			RK3328_CLKGATE_CON(8), 3, GFLAGS),
372
-	GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0,
362
+	GATE(0, "pclk_phy_pre", "pclk_bus_pre", CLK_IS_CRITICAL,
373363 			RK3328_CLKGATE_CON(8), 4, GFLAGS),
374364 
375365 	COMPOSITE(SCLK_TSP, "clk_tsp", mux_2plls_p, 0,
....@@ -385,7 +375,7 @@
385375 	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
386376 			RK3328_CLKSEL_CON(7), 0,
387377 			RK3328_CLKGATE_CON(1), 2, GFLAGS,
388
-			&rk3328_i2s0_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
378
+			&rk3328_i2s0_fracmux),
389379 	GATE(SCLK_I2S0, "clk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
390380 			RK3328_CLKGATE_CON(1), 3, GFLAGS),
391381 
....@@ -395,7 +385,7 @@
395385 	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
396386 			RK3328_CLKSEL_CON(9), 0,
397387 			RK3328_CLKGATE_CON(1), 5, GFLAGS,
398
-			&rk3328_i2s1_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
388
+			&rk3328_i2s1_fracmux),
399389 	GATE(SCLK_I2S1, "clk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
400390 			RK3328_CLKGATE_CON(1), 6, GFLAGS),
401391 	COMPOSITE_NODIV(SCLK_I2S1_OUT, "i2s1_out", mux_i2s1out_p, 0,
....@@ -408,7 +398,7 @@
408398 	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
409399 			RK3328_CLKSEL_CON(11), 0,
410400 			RK3328_CLKGATE_CON(1), 9, GFLAGS,
411
-			&rk3328_i2s2_fracmux, RK3328_I2S_FRAC_MAX_PRATE),
401
+			&rk3328_i2s2_fracmux),
412402 	GATE(SCLK_I2S2, "clk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
413403 			RK3328_CLKGATE_CON(1), 10, GFLAGS),
414404 	COMPOSITE_NODIV(SCLK_I2S2_OUT, "i2s2_out", mux_i2s2out_p, 0,
....@@ -421,7 +411,7 @@
421411 	COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
422412 			RK3328_CLKSEL_CON(13), 0,
423413 			RK3328_CLKGATE_CON(1), 13, GFLAGS,
424
-			&rk3328_spdif_fracmux, RK3328_SPDIF_FRAC_MAX_PRATE),
414
+			&rk3328_spdif_fracmux),
425415 
426416 	/* PD_UART */
427417 	COMPOSITE(0, "clk_uart0_div", mux_2plls_u480m_p, 0,
....@@ -436,15 +426,15 @@
436426 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
437427 			RK3328_CLKSEL_CON(15), 0,
438428 			RK3328_CLKGATE_CON(1), 15, GFLAGS,
439
-			&rk3328_uart0_fracmux, RK3328_UART_FRAC_MAX_PRATE),
429
+			&rk3328_uart0_fracmux),
440430 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
441431 			RK3328_CLKSEL_CON(17), 0,
442432 			RK3328_CLKGATE_CON(2), 1, GFLAGS,
443
-			&rk3328_uart1_fracmux, RK3328_UART_FRAC_MAX_PRATE),
433
+			&rk3328_uart1_fracmux),
444434 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
445435 			RK3328_CLKSEL_CON(19), 0,
446436 			RK3328_CLKGATE_CON(2), 3, GFLAGS,
447
-			&rk3328_uart2_fracmux, RK3328_UART_FRAC_MAX_PRATE),
437
+			&rk3328_uart2_fracmux),
448438 
449439 	/*
450440 	 * Clock-Architecture Diagram 4
....@@ -518,9 +508,9 @@
518508 			RK3328_CLKGATE_CON(24), 0, GFLAGS),
519509 	GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", CLK_SET_RATE_PARENT,
520510 			RK3328_CLKGATE_CON(24), 1, GFLAGS),
521
-	GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", 0,
511
+	GATE(0, "aclk_rkvdec_niu", "aclk_rkvdec_pre", CLK_IS_CRITICAL,
522512 			RK3328_CLKGATE_CON(24), 2, GFLAGS),
523
-	GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", 0,
513
+	GATE(0, "hclk_rkvdec_niu", "hclk_rkvdec_pre", CLK_IS_CRITICAL,
524514 			RK3328_CLKGATE_CON(24), 3, GFLAGS),
525515 
526516 	COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_4plls_p, 0,
....@@ -540,9 +530,9 @@
540530 			RK3328_CLKGATE_CON(23), 0, GFLAGS),
541531 	GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", CLK_SET_RATE_PARENT,
542532 			RK3328_CLKGATE_CON(23), 1, GFLAGS),
543
-	GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", 0,
533
+	GATE(0, "aclk_vpu_niu", "aclk_vpu_pre", CLK_IS_CRITICAL,
544534 			RK3328_CLKGATE_CON(23), 2, GFLAGS),
545
-	GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", 0,
535
+	GATE(0, "hclk_vpu_niu", "hclk_vpu_pre", CLK_IS_CRITICAL,
546536 			RK3328_CLKGATE_CON(23), 3, GFLAGS),
547537 
548538 	COMPOSITE(ACLK_RKVENC, "aclk_rkvenc", mux_4plls_p, 0,
....@@ -555,9 +545,9 @@
555545 	FACTOR_GATE(0, "hclk_venc", "sclk_venc_core", 0, 1, 4,
556546 			RK3328_CLKGATE_CON(11), 4, GFLAGS),
557547 
558
-	GATE(0, "aclk_rkvenc_niu", "sclk_venc_core", 0,
548
+	GATE(0, "aclk_rkvenc_niu", "sclk_venc_core", CLK_IS_CRITICAL,
559549 			RK3328_CLKGATE_CON(25), 0, GFLAGS),
560
-	GATE(0, "hclk_rkvenc_niu", "hclk_venc", 0,
550
+	GATE(0, "hclk_rkvenc_niu", "hclk_venc", CLK_IS_CRITICAL,
561551 			RK3328_CLKGATE_CON(25), 1, GFLAGS),
562552 	GATE(ACLK_H265, "aclk_h265", "sclk_venc_core", 0,
563553 			RK3328_CLKGATE_CON(25), 2, GFLAGS),
....@@ -597,7 +587,7 @@
597587 	GATE(SCLK_HDMI_SFC, "sclk_hdmi_sfc", "xin24m", 0,
598588 			RK3328_CLKGATE_CON(5), 4, GFLAGS),
599589 
600
-	COMPOSITE_NODIV(0, "clk_cif_src", mux_hdmiphy_gpll_p, 0,
590
+	COMPOSITE_NODIV(0, "clk_cif_src", mux_2plls_p, 0,
601591 			RK3328_CLKSEL_CON(42), 7, 1, MFLAGS,
602592 			RK3328_CLKGATE_CON(5), 3, GFLAGS),
603593 	COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cif_out", mux_sclk_cif_p, CLK_SET_RATE_PARENT,
....@@ -616,21 +606,21 @@
616606 	 */
617607 
618608 	/* PD_PERI */
619
-	GATE(0, "gpll_peri", "gpll", CLK_IGNORE_UNUSED,
609
+	GATE(0, "gpll_peri", "gpll", CLK_IS_CRITICAL,
620610 			RK3328_CLKGATE_CON(4), 0, GFLAGS),
621
-	GATE(0, "cpll_peri", "cpll", CLK_IGNORE_UNUSED,
611
+	GATE(0, "cpll_peri", "cpll", CLK_IS_CRITICAL,
622612 			RK3328_CLKGATE_CON(4), 1, GFLAGS),
623
-	GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IGNORE_UNUSED,
613
+	GATE(0, "hdmiphy_peri", "hdmiphy", CLK_IS_CRITICAL,
624614 			RK3328_CLKGATE_CON(4), 2, GFLAGS),
625
-	COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, 0,
615
+	COMPOSITE_NOGATE(ACLK_PERI_PRE, "aclk_peri_pre", mux_aclk_peri_pre_p, CLK_IS_CRITICAL,
626616 			RK3328_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS),
627
-	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
617
+	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
628618 			RK3328_CLKSEL_CON(29), 0, 2, DFLAGS,
629619 			RK3328_CLKGATE_CON(10), 2, GFLAGS),
630
-	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED,
620
+	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
631621 			RK3328_CLKSEL_CON(29), 4, 3, DFLAGS,
632622 			RK3328_CLKGATE_CON(10), 1, GFLAGS),
633
-	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT,
623
+	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
634624 			RK3328_CLKGATE_CON(10), 0, GFLAGS),
635625 
636626 	COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_2plls_24m_u480m_p, 0,
....@@ -715,30 +705,30 @@
715705 
716706 	/* PD_VOP */
717707 	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(21), 10, GFLAGS),
718
-	GATE(0, "aclk_rga_niu", "aclk_rga_pre", 0, RK3328_CLKGATE_CON(22), 3, GFLAGS),
708
+	GATE(0, "aclk_rga_niu", "aclk_rga_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(22), 3, GFLAGS),
719709 	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 2, GFLAGS),
720
-	GATE(0, "aclk_vop_niu", "aclk_vop_pre", 0, RK3328_CLKGATE_CON(21), 4, GFLAGS),
710
+	GATE(0, "aclk_vop_niu", "aclk_vop_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 4, GFLAGS),
721711 
722712 	GATE(ACLK_IEP, "aclk_iep", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 6, GFLAGS),
723713 	GATE(ACLK_CIF, "aclk_cif", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 8, GFLAGS),
724714 	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 15, GFLAGS),
725
-	GATE(0, "aclk_vio_niu", "aclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 2, GFLAGS),
715
+	GATE(0, "aclk_vio_niu", "aclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(22), 2, GFLAGS),
726716 
727717 	GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 3, GFLAGS),
728
-	GATE(0, "hclk_vop_niu", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 5, GFLAGS),
718
+	GATE(0, "hclk_vop_niu", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 5, GFLAGS),
729719 	GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 7, GFLAGS),
730720 	GATE(HCLK_CIF, "hclk_cif", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 9, GFLAGS),
731721 	GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 11, GFLAGS),
732
-	GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(21), 12, GFLAGS),
733
-	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 13, GFLAGS),
734
-	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(21), 14, GFLAGS),
722
+	GATE(0, "hclk_ahb1tom", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 12, GFLAGS),
723
+	GATE(0, "pclk_vio_h2p", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 13, GFLAGS),
724
+	GATE(0, "hclk_vio_h2p", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(21), 14, GFLAGS),
735725 	GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 0, GFLAGS),
736
-	GATE(0, "hclk_vio_niu", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 1, GFLAGS),
726
+	GATE(0, "hclk_vio_niu", "hclk_vio_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(22), 1, GFLAGS),
737727 	GATE(PCLK_HDMI, "pclk_hdmi", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 4, GFLAGS),
738728 	GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK3328_CLKGATE_CON(22), 5, GFLAGS),
739729 
740730 	/* PD_PERI */
741
-	GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
731
+	GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(19), 11, GFLAGS),
742732 	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
743733 
744734 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
....@@ -748,26 +738,26 @@
748738 	GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 6, GFLAGS),
749739 	GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 7, GFLAGS),
750740 	GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 8, GFLAGS),
751
-	GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 9, GFLAGS),
752
-	GATE(0, "hclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 12, GFLAGS),
753
-	GATE(0, "pclk_peri_niu", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 13, GFLAGS),
741
+	GATE(HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(19), 9, GFLAGS),
742
+	GATE(0, "hclk_peri_niu", "hclk_peri", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(19), 12, GFLAGS),
743
+	GATE(0, "pclk_peri_niu", "hclk_peri", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(19), 13, GFLAGS),
754744 
755745 	/* PD_GMAC */
756746 	GATE(ACLK_MAC2PHY, "aclk_mac2phy", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 0, GFLAGS),
757747 	GATE(ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 2, GFLAGS),
758
-	GATE(0, "aclk_gmac_niu", "aclk_gmac", 0, RK3328_CLKGATE_CON(26), 4, GFLAGS),
748
+	GATE(0, "aclk_gmac_niu", "aclk_gmac", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(26), 4, GFLAGS),
759749 	GATE(PCLK_MAC2PHY, "pclk_mac2phy", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 1, GFLAGS),
760750 	GATE(PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 3, GFLAGS),
761
-	GATE(0, "pclk_gmac_niu", "pclk_gmac", 0, RK3328_CLKGATE_CON(26), 5, GFLAGS),
751
+	GATE(0, "pclk_gmac_niu", "pclk_gmac", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(26), 5, GFLAGS),
762752 
763753 	/* PD_BUS */
764
-	GATE(0, "aclk_bus_niu", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 12, GFLAGS),
754
+	GATE(0, "aclk_bus_niu", "aclk_bus_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 12, GFLAGS),
765755 	GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 11, GFLAGS),
766756 	GATE(ACLK_TSP, "aclk_tsp", "aclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 12, GFLAGS),
767
-	GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 0, GFLAGS),
757
+	GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 0, GFLAGS),
768758 	GATE(ACLK_DMAC, "aclk_dmac_bus", "aclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 1, GFLAGS),
769759 
770
-	GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 2, GFLAGS),
760
+	GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 2, GFLAGS),
771761 	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 3, GFLAGS),
772762 	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 4, GFLAGS),
773763 	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 5, GFLAGS),
....@@ -775,17 +765,17 @@
775765 	GATE(HCLK_TSP, "hclk_tsp", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(17), 11, GFLAGS),
776766 	GATE(HCLK_CRYPTO_MST, "hclk_crypto_mst", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 7, GFLAGS),
777767 	GATE(HCLK_CRYPTO_SLV, "hclk_crypto_slv", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 8, GFLAGS),
778
-	GATE(0, "hclk_bus_niu", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(15), 13, GFLAGS),
768
+	GATE(0, "hclk_bus_niu", "hclk_bus_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 13, GFLAGS),
779769 	GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_pre", 0, RK3328_CLKGATE_CON(28), 0, GFLAGS),
780770 
781
-	GATE(0, "pclk_bus_niu", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 14, GFLAGS),
771
+	GATE(0, "pclk_bus_niu", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 14, GFLAGS),
782772 	GATE(0, "pclk_efuse", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(15), 9, GFLAGS),
783773 	GATE(0, "pclk_otp", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 4, GFLAGS),
784774 	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS),
785775 	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 0, GFLAGS),
786776 	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 1, GFLAGS),
787777 	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 2, GFLAGS),
788
-	GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 3, GFLAGS),
778
+	GATE(PCLK_TIMER, "pclk_timer0", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(16), 3, GFLAGS),
789779 	GATE(0, "pclk_stimer", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 4, GFLAGS),
790780 	GATE(PCLK_SPI, "pclk_spi", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 5, GFLAGS),
791781 	GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS),
....@@ -798,23 +788,25 @@
798788 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS),
799789 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS),
800790 	GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
801
-	GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS),
802
-	GATE(0, "pclk_cru", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 4, GFLAGS),
803
-	GATE(PCLK_ACODEC, "pclk_acodec", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
804
-	GATE(0, "pclk_sgrf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 6, GFLAGS),
791
+	GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(17), 0, GFLAGS),
792
+	GATE(0, "pclk_cru", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(17), 4, GFLAGS),
793
+	GATE(0, "pclk_sgrf", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(17), 6, GFLAGS),
805794 	GATE(0, "pclk_sim", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 10, GFLAGS),
806795 	GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus", 0, RK3328_CLKGATE_CON(17), 15, GFLAGS),
807
-	GATE(0, "pclk_pmu", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(28), 3, GFLAGS),
796
+	GATE(0, "pclk_pmu", "pclk_bus", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(28), 3, GFLAGS),
797
+
798
+	/* Watchdog pclk is controlled from the secure GRF */
799
+	SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
808800 
809801 	GATE(PCLK_USB3PHY_OTG, "pclk_usb3phy_otg", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 1, GFLAGS),
810802 	GATE(PCLK_USB3PHY_PIPE, "pclk_usb3phy_pipe", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(28), 2, GFLAGS),
811803 	GATE(PCLK_USB3_GRF, "pclk_usb3_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 2, GFLAGS),
812804 	GATE(PCLK_USB2_GRF, "pclk_usb2_grf", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 14, GFLAGS),
813
-	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 13, GFLAGS),
814
-	GATE(0, "pclk_acodecphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 5, GFLAGS),
805
+	GATE(0, "pclk_ddrphy", "pclk_phy_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(17), 13, GFLAGS),
806
+	GATE(PCLK_ACODECPHY, "pclk_acodecphy", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(17), 5, GFLAGS),
815807 	GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 7, GFLAGS),
816808 	GATE(0, "pclk_vdacphy", "pclk_phy_pre", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 8, GFLAGS),
817
-	GATE(0, "pclk_phy_niu", "pclk_phy_pre", 0, RK3328_CLKGATE_CON(15), 15, GFLAGS),
809
+	GATE(0, "pclk_phy_niu", "pclk_phy_pre", CLK_IS_CRITICAL, RK3328_CLKGATE_CON(15), 15, GFLAGS),
818810 
819811 	/* PD_MMC */
820812 	MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc",
....@@ -838,61 +830,11 @@
838830 	    RK3328_SDMMC_EXT_CON1, 1),
839831 };
840832 
841
-static const char *const rk3328_critical_clocks[] __initconst = {
842
-	"aclk_bus",
843
-	"aclk_bus_niu",
844
-	"pclk_bus",
845
-	"pclk_bus_niu",
846
-	"hclk_bus",
847
-	"hclk_bus_niu",
848
-	"aclk_peri",
849
-	"hclk_peri",
850
-	"hclk_peri_niu",
851
-	"pclk_peri",
852
-	"pclk_peri_niu",
853
-	"pclk_dbg",
854
-	"aclk_core_niu",
855
-	"aclk_gic400",
856
-	"aclk_intmem",
857
-	"hclk_rom",
858
-	"pclk_grf",
859
-	"pclk_cru",
860
-	"pclk_sgrf",
861
-	"pclk_timer0",
862
-	"clk_timer0",
863
-	"pclk_ddr_msch",
864
-	"pclk_ddr_mon",
865
-	"pclk_ddr_grf",
866
-	"clk_ddrupctl",
867
-	"clk_ddrmsch",
868
-	"hclk_ahb1tom",
869
-	"clk_jtag",
870
-	"pclk_ddrphy",
871
-	"pclk_pmu",
872
-	"hclk_otg_pmu",
873
-	"aclk_rga_niu",
874
-	"pclk_vio_h2p",
875
-	"hclk_vio_h2p",
876
-	"aclk_vio_niu",
877
-	"hclk_vio_niu",
878
-	"aclk_vop_niu",
879
-	"hclk_vop_niu",
880
-	"aclk_gpu_niu",
881
-	"aclk_rkvdec_niu",
882
-	"hclk_rkvdec_niu",
883
-	"aclk_vpu_niu",
884
-	"hclk_vpu_niu",
885
-	"aclk_rkvenc_niu",
886
-	"hclk_rkvenc_niu",
887
-	"aclk_gmac_niu",
888
-	"pclk_gmac_niu",
889
-	"pclk_phy_niu",
890
-};
891
-
892833 static void __init rk3328_clk_init(struct device_node *np)
893834 {
894835 	struct rockchip_clk_provider *ctx;
895836 	void __iomem *reg_base;
837
+	struct clk **clks;
896838 
897839 	reg_base = of_iomap(np, 0);
898840 	if (!reg_base) {
....@@ -906,17 +848,16 @@
906848 		iounmap(reg_base);
907849 		return;
908850 	}
851
+	clks = ctx->clk_data.clks;
909852 
910853 	rockchip_clk_register_plls(ctx, rk3328_pll_clks,
911854 				   ARRAY_SIZE(rk3328_pll_clks),
912855 				   RK3328_GRF_SOC_STATUS0);
913856 	rockchip_clk_register_branches(ctx, rk3328_clk_branches,
914857 				       ARRAY_SIZE(rk3328_clk_branches));
915
-	rockchip_clk_protect_critical(rk3328_critical_clocks,
916
-				      ARRAY_SIZE(rk3328_critical_clocks));
917858 
918859 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
919
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
860
+				     4, clks[PLL_APLL], clks[PLL_GPLL],
920861 				     &rk3328_cpuclk_data, rk3328_cpuclk_rates,
921862 				     ARRAY_SIZE(rk3328_cpuclk_rates));
922863 
....@@ -928,3 +869,31 @@
928869 	rockchip_clk_of_add_provider(np, ctx);
929870 }
930871 CLK_OF_DECLARE(rk3328_cru, "rockchip,rk3328-cru", rk3328_clk_init);
872
+
873
+static int __init clk_rk3328_probe(struct platform_device *pdev)
874
+{
875
+	struct device_node *np = pdev->dev.of_node;
876
+
877
+	rk3328_clk_init(np);
878
+
879
+	return 0;
880
+}
881
+
882
+static const struct of_device_id clk_rk3328_match_table[] = {
883
+	{
884
+		.compatible = "rockchip,rk3328-cru",
885
+	},
886
+	{ }
887
+};
888
+MODULE_DEVICE_TABLE(of, clk_rk3328_match_table);
889
+
890
+static struct platform_driver clk_rk3328_driver = {
891
+	.driver		= {
892
+		.name	= "clk-rk3328",
893
+		.of_match_table = clk_rk3328_match_table,
894
+	},
895
+};
896
+builtin_platform_driver_probe(clk_rk3328_driver, clk_rk3328_probe);
897
+
898
+MODULE_DESCRIPTION("Rockchip RK3328 Clock Driver");
899
+MODULE_LICENSE("GPL");