add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clk/renesas/r8a77995-cpg-mssr.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0
1
2
 /*
2
3
  * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
3
4
  *
..
..
@@ -7,10 +8,6 @@
7
8
  *
8
9
  * Copyright (C) 2015 Glider bvba
9
10
  * Copyright (C) 2015 Renesas Electronics Corp.
10
- *
11
- * This program is free software; you can redistribute it and/or modify
12
- * it under the terms of the GNU General Public License as published by
13
- * the Free Software Foundation; version 2 of the License.
14
11
  */
15
12
 
16
13
 #include <linux/device.h>
..
..
@@ -25,7 +22,7 @@
25
22
 
26
23
 enum clk_ids {
27
24
 	/* Core Clock Outputs exported to DT */
28
-	LAST_DT_CORE_CLK = R8A77995_CLK_CP,
25
+	LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
29
26
 
30
27
 	/* External Input Clocks */
31
28
 	CLK_EXTAL,
..
..
@@ -45,7 +42,8 @@
45
42
 	CLK_S2,
46
43
 	CLK_S3,
47
44
 	CLK_SDSRC,
48
-	CLK_SSPSRC,
45
+	CLK_RINT,
46
+	CLK_OCO,
49
47
 
50
48
 	/* Module Clocks */
51
49
 	MOD_CLK_BASE
..
..
@@ -72,6 +70,10 @@
72
70
 	DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
73
71
 	DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
74
72
 
73
+	DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
74
+
75
+	DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),
76
+
75
77
 	/* Core Clock Outputs */
76
78
 	DEF_FIXED("za2",       R8A77995_CLK_ZA2,   CLK_PLL0D3,     2, 1),
77
79
 	DEF_FIXED("z2",        R8A77995_CLK_Z2,    CLK_PLL0D3,     1, 1),
..
..
@@ -90,9 +92,11 @@
90
92
 	DEF_FIXED("s3d4",      R8A77995_CLK_S3D4,  CLK_S3,         4, 1),
91
93
 
92
94
 	DEF_FIXED("cl",        R8A77995_CLK_CL,    CLK_PLL1,      48, 1),
95
+	DEF_FIXED("cr",        R8A77995_CLK_CR,    CLK_PLL1D2,     2, 1),
93
96
 	DEF_FIXED("cp",        R8A77995_CLK_CP,    CLK_EXTAL,      2, 1),
94
-	DEF_FIXED("osc",       R8A77995_CLK_OSC,   CLK_EXTAL,    384, 1),
95
-	DEF_FIXED("r",         R8A77995_CLK_R,     CLK_EXTAL,   1536, 1),
97
+	DEF_FIXED("cpex",      R8A77995_CLK_CPEX,  CLK_EXTAL,      4, 1),
98
+
99
+	DEF_DIV6_RO("osc",     R8A77995_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
96
100
 
97
101
 	DEF_GEN3_PE("s1d4c",   R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
98
102
 	DEF_GEN3_PE("s3d1c",   R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
..
..
@@ -103,6 +107,8 @@
103
107
 
104
108
 	DEF_DIV6P1("canfd",    R8A77995_CLK_CANFD, CLK_PLL0D3,    0x244),
105
109
 	DEF_DIV6P1("mso",      R8A77995_CLK_MSO,   CLK_PLL1D2,    0x014),
110
+
111
+	DEF_GEN3_RCKSEL("r",   R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
106
112
 };
107
113
 
108
114
 static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
..
..
@@ -118,6 +124,7 @@
118
124
 	DEF_MOD("sys-dmac2",		 217,	R8A77995_CLK_S3D1),
119
125
 	DEF_MOD("sys-dmac1",		 218,	R8A77995_CLK_S3D1),
120
126
 	DEF_MOD("sys-dmac0",		 219,	R8A77995_CLK_S3D1),
127
+	DEF_MOD("sceg-pub",		 229,	R8A77995_CLK_CR),
121
128
 	DEF_MOD("cmt3",			 300,	R8A77995_CLK_R),
122
129
 	DEF_MOD("cmt2",			 301,	R8A77995_CLK_R),
123
130
 	DEF_MOD("cmt1",			 302,	R8A77995_CLK_R),
..
..
@@ -129,7 +136,7 @@
129
136
 	DEF_MOD("rwdt",			 402,	R8A77995_CLK_R),
130
137
 	DEF_MOD("intc-ex",		 407,	R8A77995_CLK_CP),
131
138
 	DEF_MOD("intc-ap",		 408,	R8A77995_CLK_S1D2),
132
-	DEF_MOD("audmac0",		 502,	R8A77995_CLK_S3D1),
139
+	DEF_MOD("audmac0",		 502,	R8A77995_CLK_S1D2),
133
140
 	DEF_MOD("hscif3",		 517,	R8A77995_CLK_S3D1C),
134
141
 	DEF_MOD("hscif0",		 520,	R8A77995_CLK_S3D1C),
135
142
 	DEF_MOD("thermal",		 522,	R8A77995_CLK_CP),
..
..
@@ -142,12 +149,11 @@
142
149
 	DEF_MOD("vspbs",		 627,	R8A77995_CLK_S0D1),
143
150
 	DEF_MOD("ehci0",		 703,	R8A77995_CLK_S3D2),
144
151
 	DEF_MOD("hsusb",		 704,	R8A77995_CLK_S3D2),
152
+	DEF_MOD("cmm1",			 710,	R8A77995_CLK_S1D1),
153
+	DEF_MOD("cmm0",			 711,	R8A77995_CLK_S1D1),
145
154
 	DEF_MOD("du1",			 723,	R8A77995_CLK_S1D1),
146
155
 	DEF_MOD("du0",			 724,	R8A77995_CLK_S1D1),
147
156
 	DEF_MOD("lvds",			 727,	R8A77995_CLK_S2D1),
148
-	DEF_MOD("vin7",			 804,	R8A77995_CLK_S1D2),
149
-	DEF_MOD("vin6",			 805,	R8A77995_CLK_S1D2),
150
-	DEF_MOD("vin5",			 806,	R8A77995_CLK_S1D2),
151
157
 	DEF_MOD("vin4",			 807,	R8A77995_CLK_S1D2),
152
158
 	DEF_MOD("etheravb",		 812,	R8A77995_CLK_S3D2),
153
159
 	DEF_MOD("imr0",			 823,	R8A77995_CLK_S1D2),
..
..
@@ -178,9 +184,9 @@
178
184
 };
179
185
 
180
186
 static const unsigned int r8a77995_crit_mod_clks[] __initconst = {
187
+	MOD_CLK_ID(402),	/* RWDT */
181
188
 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
182
189
 };
183
-
184
190
 
185
191
 /*
186
192
  * CPG Clock Data
..
..
@@ -190,14 +196,14 @@
190
196
  * MD19		EXTAL (MHz)	PLL0		PLL1		PLL3
191
197
  *--------------------------------------------------------------------
192
198
  * 0		48 x 1		x250/4		x100/3		x100/3
193
- * 1		48 x 1		x250/4		x100/3		x116/6
199
+ * 1		48 x 1		x250/4		x100/3		x58/3
194
200
  */
195
201
 #define CPG_PLL_CONFIG_INDEX(md)	(((md) & BIT(19)) >> 19)
196
202
 
197
203
 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
198
204
 	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
199
205
 	{ 1,		100,	3,	100,	3,	},
200
-	{ 1,		100,	3,	116,	6,	},
206
+	{ 1,		100,	3,	58,	3,	},
201
207
 };
202
208
 
203
209
 static int __init r8a77995_cpg_mssr_init(struct device *dev)