hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/clk/renesas/r8a77965-cpg-mssr.c
....@@ -3,6 +3,7 @@
33 * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
44 *
55 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6
+ * Copyright (C) 2019 Renesas Electronics Corp.
67 *
78 * Based on r8a7795-cpg-mssr.c
89 *
....@@ -42,6 +43,7 @@
4243 CLK_S3,
4344 CLK_SDSRC,
4445 CLK_SSPSRC,
46
+ CLK_RPCSRC,
4547 CLK_RINT,
4648
4749 /* Module Clocks */
....@@ -67,9 +69,17 @@
6769 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
6870 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
6971 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
72
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
73
+
74
+ DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
75
+ CLK_RPCSRC),
76
+ DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
77
+ R8A77965_CLK_RPC),
78
+
79
+ DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
7080
7181 /* Core Clock Outputs */
72
- DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
82
+ DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
7383 DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
7484 DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
7585 DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
....@@ -96,21 +106,23 @@
96106 DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
97107 DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
98108
99
- DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
109
+ DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
110
+ DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
100111 DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
112
+ DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
101113
102114 DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
103115 DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
104116 DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014),
105117 DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
106118
107
- DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
108
- DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
119
+ DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8),
109120
110121 DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
111122 };
112123
113124 static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
125
+ DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
114126 DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
115127 DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
116128 DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
....@@ -120,14 +132,16 @@
120132 DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
121133 DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
122134 DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
123
- DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
124
- DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
135
+ DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
136
+ DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
125137 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
138
+ DEF_MOD("sceg-pub", 229, R8A77965_CLK_CR),
126139
127140 DEF_MOD("cmt3", 300, R8A77965_CLK_R),
128141 DEF_MOD("cmt2", 301, R8A77965_CLK_R),
129142 DEF_MOD("cmt1", 302, R8A77965_CLK_R),
130143 DEF_MOD("cmt0", 303, R8A77965_CLK_R),
144
+ DEF_MOD("tpu0", 304, R8A77965_CLK_S3D4),
131145 DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
132146 DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
133147 DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
....@@ -143,16 +157,16 @@
143157 DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
144158 DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
145159
146
- DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
147
- DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
148
- DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
149
- DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
150
- DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
151
- DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
152
- DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
153
- DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
154
- DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
155
- DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
160
+ DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
161
+ DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
162
+ DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),
163
+ DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),
164
+ DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),
165
+ DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),
166
+ DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),
167
+ DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),
168
+ DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),
169
+ DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),
156170 DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
157171 DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
158172 DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
....@@ -172,9 +186,12 @@
172186 DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
173187 DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
174188
175
- DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
176
- DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
177
- DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
189
+ DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
190
+ DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
191
+ DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
192
+ DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1),
193
+ DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1),
194
+ DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1),
178195 DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
179196 DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
180197 DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
....@@ -192,6 +209,7 @@
192209 DEF_MOD("vin1", 810, R8A77965_CLK_S0D2),
193210 DEF_MOD("vin0", 811, R8A77965_CLK_S0D2),
194211 DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6),
212
+ DEF_MOD("sata0", 815, R8A77965_CLK_S3D2),
195213 DEF_MOD("imr1", 822, R8A77965_CLK_S0D2),
196214 DEF_MOD("imr0", 823, R8A77965_CLK_S0D2),
197215
....@@ -206,6 +224,7 @@
206224 DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
207225 DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
208226 DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
227
+ DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2),
209228 DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
210229 DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
211230 DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
....@@ -244,6 +263,7 @@
244263 };
245264
246265 static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
266
+ MOD_CLK_ID(402), /* RWDT */
247267 MOD_CLK_ID(408), /* INTC-AP (GIC) */
248268 };
249269
....@@ -252,25 +272,25 @@
252272 */
253273
254274 /*
255
- * MD EXTAL PLL0 PLL1 PLL3 PLL4
275
+ * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
256276 * 14 13 19 17 (MHz)
257
- *-----------------------------------------------------------
258
- * 0 0 0 0 16.66 x 1 x180 x192 x192 x144
259
- * 0 0 0 1 16.66 x 1 x180 x192 x128 x144
277
+ *-----------------------------------------------------------------
278
+ * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
279
+ * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
260280 * 0 0 1 0 Prohibited setting
261
- * 0 0 1 1 16.66 x 1 x180 x192 x192 x144
262
- * 0 1 0 0 20 x 1 x150 x160 x160 x120
263
- * 0 1 0 1 20 x 1 x150 x160 x106 x120
281
+ * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
282
+ * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
283
+ * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
264284 * 0 1 1 0 Prohibited setting
265
- * 0 1 1 1 20 x 1 x150 x160 x160 x120
266
- * 1 0 0 0 25 x 1 x120 x128 x128 x96
267
- * 1 0 0 1 25 x 1 x120 x128 x84 x96
285
+ * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
286
+ * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
287
+ * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
268288 * 1 0 1 0 Prohibited setting
269
- * 1 0 1 1 25 x 1 x120 x128 x128 x96
270
- * 1 1 0 0 33.33 / 2 x180 x192 x192 x144
271
- * 1 1 0 1 33.33 / 2 x180 x192 x128 x144
289
+ * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
290
+ * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
291
+ * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
272292 * 1 1 1 0 Prohibited setting
273
- * 1 1 1 1 33.33 / 2 x180 x192 x192 x144
293
+ * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
274294 */
275295 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
276296 (((md) & BIT(13)) >> 11) | \
....@@ -278,23 +298,23 @@
278298 (((md) & BIT(17)) >> 17))
279299
280300 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
281
- /* EXTAL div PLL1 mult/div PLL3 mult/div */
282
- { 1, 192, 1, 192, 1, },
283
- { 1, 192, 1, 128, 1, },
284
- { 0, /* Prohibited setting */ },
285
- { 1, 192, 1, 192, 1, },
286
- { 1, 160, 1, 160, 1, },
287
- { 1, 160, 1, 106, 1, },
288
- { 0, /* Prohibited setting */ },
289
- { 1, 160, 1, 160, 1, },
290
- { 1, 128, 1, 128, 1, },
291
- { 1, 128, 1, 84, 1, },
292
- { 0, /* Prohibited setting */ },
293
- { 1, 128, 1, 128, 1, },
294
- { 2, 192, 1, 192, 1, },
295
- { 2, 192, 1, 128, 1, },
296
- { 0, /* Prohibited setting */ },
297
- { 2, 192, 1, 192, 1, },
301
+ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
302
+ { 1, 192, 1, 192, 1, 16, },
303
+ { 1, 192, 1, 128, 1, 16, },
304
+ { 0, /* Prohibited setting */ },
305
+ { 1, 192, 1, 192, 1, 16, },
306
+ { 1, 160, 1, 160, 1, 19, },
307
+ { 1, 160, 1, 106, 1, 19, },
308
+ { 0, /* Prohibited setting */ },
309
+ { 1, 160, 1, 160, 1, 19, },
310
+ { 1, 128, 1, 128, 1, 24, },
311
+ { 1, 128, 1, 84, 1, 24, },
312
+ { 0, /* Prohibited setting */ },
313
+ { 1, 128, 1, 128, 1, 24, },
314
+ { 2, 192, 1, 192, 1, 32, },
315
+ { 2, 192, 1, 128, 1, 32, },
316
+ { 0, /* Prohibited setting */ },
317
+ { 2, 192, 1, 192, 1, 32, },
298318 };
299319
300320 static int __init r8a77965_cpg_mssr_init(struct device *dev)
....@@ -314,7 +334,7 @@
314334 }
315335
316336 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
317
-};
337
+}
318338
319339 const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {
320340 /* Core Clocks */