.. | .. |
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3 | 3 | * r8a77965 Clock Pulse Generator / Module Standby and Software Reset |
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4 | 4 | * |
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5 | 5 | * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> |
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| 6 | + * Copyright (C) 2019 Renesas Electronics Corp. |
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6 | 7 | * |
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7 | 8 | * Based on r8a7795-cpg-mssr.c |
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8 | 9 | * |
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.. | .. |
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42 | 43 | CLK_S3, |
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43 | 44 | CLK_SDSRC, |
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44 | 45 | CLK_SSPSRC, |
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| 46 | + CLK_RPCSRC, |
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45 | 47 | CLK_RINT, |
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46 | 48 | |
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47 | 49 | /* Module Clocks */ |
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.. | .. |
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67 | 69 | DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), |
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68 | 70 | DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), |
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69 | 71 | DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), |
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| 72 | + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), |
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| 73 | + |
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| 74 | + DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, |
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| 75 | + CLK_RPCSRC), |
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| 76 | + DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, |
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| 77 | + R8A77965_CLK_RPC), |
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| 78 | + |
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| 79 | + DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), |
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70 | 80 | |
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71 | 81 | /* Core Clock Outputs */ |
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72 | | - DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), |
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| 82 | + DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), |
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73 | 83 | DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), |
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74 | 84 | DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), |
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75 | 85 | DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), |
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.. | .. |
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96 | 106 | DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268), |
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97 | 107 | DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c), |
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98 | 108 | |
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99 | | - DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
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| 109 | + DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
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| 110 | + DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1), |
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100 | 111 | DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1), |
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| 112 | + DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1), |
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101 | 113 | |
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102 | 114 | DEF_DIV6P1("canfd", R8A77965_CLK_CANFD, CLK_PLL1_DIV4, 0x244), |
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103 | 115 | DEF_DIV6P1("csi0", R8A77965_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), |
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104 | 116 | DEF_DIV6P1("mso", R8A77965_CLK_MSO, CLK_PLL1_DIV4, 0x014), |
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105 | 117 | DEF_DIV6P1("hdmi", R8A77965_CLK_HDMI, CLK_PLL1_DIV4, 0x250), |
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106 | 118 | |
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107 | | - DEF_DIV6_RO("osc", R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), |
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108 | | - DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), |
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| 119 | + DEF_GEN3_OSC("osc", R8A77965_CLK_OSC, CLK_EXTAL, 8), |
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109 | 120 | |
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110 | 121 | DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), |
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111 | 122 | }; |
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112 | 123 | |
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113 | 124 | static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { |
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| 125 | + DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1), |
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114 | 126 | DEF_MOD("scif5", 202, R8A77965_CLK_S3D4), |
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115 | 127 | DEF_MOD("scif4", 203, R8A77965_CLK_S3D4), |
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116 | 128 | DEF_MOD("scif3", 204, R8A77965_CLK_S3D4), |
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.. | .. |
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120 | 132 | DEF_MOD("msiof2", 209, R8A77965_CLK_MSO), |
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121 | 133 | DEF_MOD("msiof1", 210, R8A77965_CLK_MSO), |
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122 | 134 | DEF_MOD("msiof0", 211, R8A77965_CLK_MSO), |
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123 | | - DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3), |
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124 | | - DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3), |
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| 135 | + DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1), |
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| 136 | + DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1), |
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125 | 137 | DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3), |
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| 138 | + DEF_MOD("sceg-pub", 229, R8A77965_CLK_CR), |
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126 | 139 | |
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127 | 140 | DEF_MOD("cmt3", 300, R8A77965_CLK_R), |
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128 | 141 | DEF_MOD("cmt2", 301, R8A77965_CLK_R), |
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129 | 142 | DEF_MOD("cmt1", 302, R8A77965_CLK_R), |
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130 | 143 | DEF_MOD("cmt0", 303, R8A77965_CLK_R), |
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| 144 | + DEF_MOD("tpu0", 304, R8A77965_CLK_S3D4), |
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131 | 145 | DEF_MOD("scif2", 310, R8A77965_CLK_S3D4), |
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132 | 146 | DEF_MOD("sdif3", 311, R8A77965_CLK_SD3), |
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133 | 147 | DEF_MOD("sdif2", 312, R8A77965_CLK_SD2), |
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.. | .. |
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143 | 157 | DEF_MOD("intc-ex", 407, R8A77965_CLK_CP), |
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144 | 158 | DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3), |
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145 | 159 | |
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146 | | - DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3), |
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147 | | - DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3), |
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148 | | - DEF_MOD("drif7", 508, R8A77965_CLK_S3D2), |
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149 | | - DEF_MOD("drif6", 509, R8A77965_CLK_S3D2), |
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150 | | - DEF_MOD("drif5", 510, R8A77965_CLK_S3D2), |
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151 | | - DEF_MOD("drif4", 511, R8A77965_CLK_S3D2), |
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152 | | - DEF_MOD("drif3", 512, R8A77965_CLK_S3D2), |
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153 | | - DEF_MOD("drif2", 513, R8A77965_CLK_S3D2), |
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154 | | - DEF_MOD("drif1", 514, R8A77965_CLK_S3D2), |
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155 | | - DEF_MOD("drif0", 515, R8A77965_CLK_S3D2), |
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| 160 | + DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2), |
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| 161 | + DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2), |
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| 162 | + DEF_MOD("drif31", 508, R8A77965_CLK_S3D2), |
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| 163 | + DEF_MOD("drif30", 509, R8A77965_CLK_S3D2), |
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| 164 | + DEF_MOD("drif21", 510, R8A77965_CLK_S3D2), |
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| 165 | + DEF_MOD("drif20", 511, R8A77965_CLK_S3D2), |
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| 166 | + DEF_MOD("drif11", 512, R8A77965_CLK_S3D2), |
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| 167 | + DEF_MOD("drif10", 513, R8A77965_CLK_S3D2), |
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| 168 | + DEF_MOD("drif01", 514, R8A77965_CLK_S3D2), |
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| 169 | + DEF_MOD("drif00", 515, R8A77965_CLK_S3D2), |
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156 | 170 | DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1), |
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157 | 171 | DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1), |
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158 | 172 | DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1), |
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.. | .. |
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172 | 186 | DEF_MOD("vspb", 626, R8A77965_CLK_S0D1), |
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173 | 187 | DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1), |
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174 | 188 | |
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175 | | - DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4), |
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176 | | - DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4), |
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177 | | - DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4), |
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| 189 | + DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2), |
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| 190 | + DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2), |
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| 191 | + DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2), |
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| 192 | + DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1), |
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| 193 | + DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1), |
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| 194 | + DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1), |
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178 | 195 | DEF_MOD("csi20", 714, R8A77965_CLK_CSI0), |
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179 | 196 | DEF_MOD("csi40", 716, R8A77965_CLK_CSI0), |
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180 | 197 | DEF_MOD("du3", 721, R8A77965_CLK_S2D1), |
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.. | .. |
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192 | 209 | DEF_MOD("vin1", 810, R8A77965_CLK_S0D2), |
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193 | 210 | DEF_MOD("vin0", 811, R8A77965_CLK_S0D2), |
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194 | 211 | DEF_MOD("etheravb", 812, R8A77965_CLK_S0D6), |
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| 212 | + DEF_MOD("sata0", 815, R8A77965_CLK_S3D2), |
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195 | 213 | DEF_MOD("imr1", 822, R8A77965_CLK_S0D2), |
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196 | 214 | DEF_MOD("imr0", 823, R8A77965_CLK_S0D2), |
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197 | 215 | |
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.. | .. |
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206 | 224 | DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2), |
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207 | 225 | DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4), |
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208 | 226 | DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4), |
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| 227 | + DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2), |
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209 | 228 | DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6), |
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210 | 229 | DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6), |
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211 | 230 | DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP), |
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.. | .. |
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244 | 263 | }; |
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245 | 264 | |
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246 | 265 | static const unsigned int r8a77965_crit_mod_clks[] __initconst = { |
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| 266 | + MOD_CLK_ID(402), /* RWDT */ |
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247 | 267 | MOD_CLK_ID(408), /* INTC-AP (GIC) */ |
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248 | 268 | }; |
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249 | 269 | |
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.. | .. |
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252 | 272 | */ |
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253 | 273 | |
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254 | 274 | /* |
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255 | | - * MD EXTAL PLL0 PLL1 PLL3 PLL4 |
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| 275 | + * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC |
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256 | 276 | * 14 13 19 17 (MHz) |
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257 | | - *----------------------------------------------------------- |
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258 | | - * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 |
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259 | | - * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 |
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| 277 | + *----------------------------------------------------------------- |
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| 278 | + * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16 |
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| 279 | + * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16 |
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260 | 280 | * 0 0 1 0 Prohibited setting |
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261 | | - * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 |
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262 | | - * 0 1 0 0 20 x 1 x150 x160 x160 x120 |
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263 | | - * 0 1 0 1 20 x 1 x150 x160 x106 x120 |
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| 281 | + * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16 |
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| 282 | + * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19 |
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| 283 | + * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19 |
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264 | 284 | * 0 1 1 0 Prohibited setting |
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265 | | - * 0 1 1 1 20 x 1 x150 x160 x160 x120 |
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266 | | - * 1 0 0 0 25 x 1 x120 x128 x128 x96 |
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267 | | - * 1 0 0 1 25 x 1 x120 x128 x84 x96 |
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| 285 | + * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19 |
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| 286 | + * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24 |
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| 287 | + * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24 |
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268 | 288 | * 1 0 1 0 Prohibited setting |
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269 | | - * 1 0 1 1 25 x 1 x120 x128 x128 x96 |
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270 | | - * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 |
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271 | | - * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 |
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| 289 | + * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24 |
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| 290 | + * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32 |
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| 291 | + * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32 |
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272 | 292 | * 1 1 1 0 Prohibited setting |
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273 | | - * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 |
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| 293 | + * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32 |
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274 | 294 | */ |
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275 | 295 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ |
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276 | 296 | (((md) & BIT(13)) >> 11) | \ |
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.. | .. |
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278 | 298 | (((md) & BIT(17)) >> 17)) |
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279 | 299 | |
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280 | 300 | static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { |
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281 | | - /* EXTAL div PLL1 mult/div PLL3 mult/div */ |
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282 | | - { 1, 192, 1, 192, 1, }, |
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283 | | - { 1, 192, 1, 128, 1, }, |
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284 | | - { 0, /* Prohibited setting */ }, |
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285 | | - { 1, 192, 1, 192, 1, }, |
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286 | | - { 1, 160, 1, 160, 1, }, |
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287 | | - { 1, 160, 1, 106, 1, }, |
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288 | | - { 0, /* Prohibited setting */ }, |
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289 | | - { 1, 160, 1, 160, 1, }, |
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290 | | - { 1, 128, 1, 128, 1, }, |
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291 | | - { 1, 128, 1, 84, 1, }, |
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292 | | - { 0, /* Prohibited setting */ }, |
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293 | | - { 1, 128, 1, 128, 1, }, |
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294 | | - { 2, 192, 1, 192, 1, }, |
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295 | | - { 2, 192, 1, 128, 1, }, |
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296 | | - { 0, /* Prohibited setting */ }, |
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297 | | - { 2, 192, 1, 192, 1, }, |
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| 301 | + /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ |
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| 302 | + { 1, 192, 1, 192, 1, 16, }, |
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| 303 | + { 1, 192, 1, 128, 1, 16, }, |
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| 304 | + { 0, /* Prohibited setting */ }, |
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| 305 | + { 1, 192, 1, 192, 1, 16, }, |
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| 306 | + { 1, 160, 1, 160, 1, 19, }, |
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| 307 | + { 1, 160, 1, 106, 1, 19, }, |
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| 308 | + { 0, /* Prohibited setting */ }, |
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| 309 | + { 1, 160, 1, 160, 1, 19, }, |
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| 310 | + { 1, 128, 1, 128, 1, 24, }, |
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| 311 | + { 1, 128, 1, 84, 1, 24, }, |
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| 312 | + { 0, /* Prohibited setting */ }, |
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| 313 | + { 1, 128, 1, 128, 1, 24, }, |
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| 314 | + { 2, 192, 1, 192, 1, 32, }, |
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| 315 | + { 2, 192, 1, 128, 1, 32, }, |
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| 316 | + { 0, /* Prohibited setting */ }, |
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| 317 | + { 2, 192, 1, 192, 1, 32, }, |
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298 | 318 | }; |
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299 | 319 | |
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300 | 320 | static int __init r8a77965_cpg_mssr_init(struct device *dev) |
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.. | .. |
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314 | 334 | } |
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315 | 335 | |
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316 | 336 | return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); |
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317 | | -}; |
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| 337 | +} |
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318 | 338 | |
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319 | 339 | const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = { |
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320 | 340 | /* Core Clocks */ |
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