add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clk/renesas/r8a77965-cpg-mssr.c
..
..
@@ -3,6 +3,7 @@
3
3
  * r8a77965 Clock Pulse Generator / Module Standby and Software Reset
4
4
  *
5
5
  * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6
+ * Copyright (C) 2019 Renesas Electronics Corp.
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7
  *
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8
  * Based on r8a7795-cpg-mssr.c
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9
  *
..
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@@ -42,6 +43,7 @@
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 	CLK_S3,
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 	CLK_SDSRC,
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 	CLK_SSPSRC,
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+	CLK_RPCSRC,
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 	CLK_RINT,
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48
 
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 	/* Module Clocks */
..
..
@@ -67,9 +69,17 @@
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 	DEF_FIXED(".s2",	CLK_S2,			CLK_PLL1_DIV2,	4, 1),
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 	DEF_FIXED(".s3",	CLK_S3,			CLK_PLL1_DIV2,	6, 1),
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71
 	DEF_FIXED(".sdsrc",	CLK_SDSRC,		CLK_PLL1_DIV2,	2, 1),
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+	DEF_BASE(".rpcsrc",	CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
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+
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+	DEF_BASE("rpc",		R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
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+		 CLK_RPCSRC),
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+	DEF_BASE("rpcd2",	R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
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+		 R8A77965_CLK_RPC),
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+
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+	DEF_GEN3_OSC(".r",	CLK_RINT,		CLK_EXTAL,	32),
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80
 
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 	/* Core Clock Outputs */
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-	DEF_BASE("z",		R8A77965_CLK_Z,		CLK_TYPE_GEN3_Z, CLK_PLL0),
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+	DEF_GEN3_Z("z",		R8A77965_CLK_Z,		CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
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 	DEF_FIXED("ztr",	R8A77965_CLK_ZTR,	CLK_PLL1_DIV2,	6, 1),
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 	DEF_FIXED("ztrd2",	R8A77965_CLK_ZTRD2,	CLK_PLL1_DIV2,	12, 1),
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 	DEF_FIXED("zt",		R8A77965_CLK_ZT,	CLK_PLL1_DIV2,	4, 1),
..
..
@@ -96,21 +106,23 @@
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 	DEF_GEN3_SD("sd2",	R8A77965_CLK_SD2,	CLK_SDSRC,	0x268),
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 	DEF_GEN3_SD("sd3",	R8A77965_CLK_SD3,	CLK_SDSRC,	0x26c),
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108
 
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-	DEF_FIXED("cl",		R8A77965_CLK_CL,	CLK_PLL1_DIV2,	48, 1),
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+	DEF_FIXED("cl",		R8A77965_CLK_CL,	CLK_PLL1_DIV2, 48, 1),
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+	DEF_FIXED("cr",         R8A77965_CLK_CR,	CLK_PLL1_DIV4,  2, 1),
100
111
 	DEF_FIXED("cp",		R8A77965_CLK_CP,	CLK_EXTAL,	2, 1),
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+	DEF_FIXED("cpex",	R8A77965_CLK_CPEX,	CLK_EXTAL,	2, 1),
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113
 
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 	DEF_DIV6P1("canfd",	R8A77965_CLK_CANFD,	CLK_PLL1_DIV4,	0x244),
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 	DEF_DIV6P1("csi0",	R8A77965_CLK_CSI0,	CLK_PLL1_DIV4,	0x00c),
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 	DEF_DIV6P1("mso",	R8A77965_CLK_MSO,	CLK_PLL1_DIV4,	0x014),
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 	DEF_DIV6P1("hdmi",	R8A77965_CLK_HDMI,	CLK_PLL1_DIV4,	0x250),
106
118
 
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-	DEF_DIV6_RO("osc",	R8A77965_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
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-	DEF_DIV6_RO("r_int",	CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
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+	DEF_GEN3_OSC("osc",	R8A77965_CLK_OSC,	CLK_EXTAL,	8),
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120
 
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 	DEF_BASE("r",		R8A77965_CLK_R,	CLK_TYPE_GEN3_R, CLK_RINT),
111
122
 };
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123
 
113
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 static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
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+	DEF_MOD("fdp1-0",		119,	R8A77965_CLK_S0D1),
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126
 	DEF_MOD("scif5",		202,	R8A77965_CLK_S3D4),
115
127
 	DEF_MOD("scif4",		203,	R8A77965_CLK_S3D4),
116
128
 	DEF_MOD("scif3",		204,	R8A77965_CLK_S3D4),
..
..
@@ -120,14 +132,16 @@
120
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 	DEF_MOD("msiof2",		209,	R8A77965_CLK_MSO),
121
133
 	DEF_MOD("msiof1",		210,	R8A77965_CLK_MSO),
122
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 	DEF_MOD("msiof0",		211,	R8A77965_CLK_MSO),
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-	DEF_MOD("sys-dmac2",		217,	R8A77965_CLK_S0D3),
124
-	DEF_MOD("sys-dmac1",		218,	R8A77965_CLK_S0D3),
135
+	DEF_MOD("sys-dmac2",		217,	R8A77965_CLK_S3D1),
136
+	DEF_MOD("sys-dmac1",		218,	R8A77965_CLK_S3D1),
125
137
 	DEF_MOD("sys-dmac0",		219,	R8A77965_CLK_S0D3),
138
+	DEF_MOD("sceg-pub",		229,	R8A77965_CLK_CR),
126
139
 
127
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 	DEF_MOD("cmt3",			300,	R8A77965_CLK_R),
128
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 	DEF_MOD("cmt2",			301,	R8A77965_CLK_R),
129
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 	DEF_MOD("cmt1",			302,	R8A77965_CLK_R),
130
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 	DEF_MOD("cmt0",			303,	R8A77965_CLK_R),
144
+	DEF_MOD("tpu0",			304,	R8A77965_CLK_S3D4),
131
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 	DEF_MOD("scif2",		310,	R8A77965_CLK_S3D4),
132
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 	DEF_MOD("sdif3",		311,	R8A77965_CLK_SD3),
133
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 	DEF_MOD("sdif2",		312,	R8A77965_CLK_SD2),
..
..
@@ -143,16 +157,16 @@
143
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 	DEF_MOD("intc-ex",		407,	R8A77965_CLK_CP),
144
158
 	DEF_MOD("intc-ap",		408,	R8A77965_CLK_S0D3),
145
159
 
146
-	DEF_MOD("audmac1",		501,	R8A77965_CLK_S0D3),
147
-	DEF_MOD("audmac0",		502,	R8A77965_CLK_S0D3),
148
-	DEF_MOD("drif7",		508,	R8A77965_CLK_S3D2),
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-	DEF_MOD("drif6",		509,	R8A77965_CLK_S3D2),
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-	DEF_MOD("drif5",		510,	R8A77965_CLK_S3D2),
151
-	DEF_MOD("drif4",		511,	R8A77965_CLK_S3D2),
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-	DEF_MOD("drif3",		512,	R8A77965_CLK_S3D2),
153
-	DEF_MOD("drif2",		513,	R8A77965_CLK_S3D2),
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-	DEF_MOD("drif1",		514,	R8A77965_CLK_S3D2),
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-	DEF_MOD("drif0",		515,	R8A77965_CLK_S3D2),
160
+	DEF_MOD("audmac1",		501,	R8A77965_CLK_S1D2),
161
+	DEF_MOD("audmac0",		502,	R8A77965_CLK_S1D2),
162
+	DEF_MOD("drif31",		508,	R8A77965_CLK_S3D2),
163
+	DEF_MOD("drif30",		509,	R8A77965_CLK_S3D2),
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+	DEF_MOD("drif21",		510,	R8A77965_CLK_S3D2),
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+	DEF_MOD("drif20",		511,	R8A77965_CLK_S3D2),
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+	DEF_MOD("drif11",		512,	R8A77965_CLK_S3D2),
167
+	DEF_MOD("drif10",		513,	R8A77965_CLK_S3D2),
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+	DEF_MOD("drif01",		514,	R8A77965_CLK_S3D2),
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+	DEF_MOD("drif00",		515,	R8A77965_CLK_S3D2),
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 	DEF_MOD("hscif4",		516,	R8A77965_CLK_S3D1),
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 	DEF_MOD("hscif3",		517,	R8A77965_CLK_S3D1),
158
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 	DEF_MOD("hscif2",		518,	R8A77965_CLK_S3D1),
..
..
@@ -172,9 +186,12 @@
172
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 	DEF_MOD("vspb",			626,	R8A77965_CLK_S0D1),
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 	DEF_MOD("vspi0",		631,	R8A77965_CLK_S0D1),
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-	DEF_MOD("ehci1",		702,	R8A77965_CLK_S3D4),
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-	DEF_MOD("ehci0",		703,	R8A77965_CLK_S3D4),
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-	DEF_MOD("hsusb",		704,	R8A77965_CLK_S3D4),
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+	DEF_MOD("ehci1",		702,	R8A77965_CLK_S3D2),
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+	DEF_MOD("ehci0",		703,	R8A77965_CLK_S3D2),
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+	DEF_MOD("hsusb",		704,	R8A77965_CLK_S3D2),
192
+	DEF_MOD("cmm3",			708,	R8A77965_CLK_S2D1),
193
+	DEF_MOD("cmm1",			710,	R8A77965_CLK_S2D1),
194
+	DEF_MOD("cmm0",			711,	R8A77965_CLK_S2D1),
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 	DEF_MOD("csi20",		714,	R8A77965_CLK_CSI0),
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 	DEF_MOD("csi40",		716,	R8A77965_CLK_CSI0),
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 	DEF_MOD("du3",			721,	R8A77965_CLK_S2D1),
..
..
@@ -192,6 +209,7 @@
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 	DEF_MOD("vin1",			810,	R8A77965_CLK_S0D2),
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 	DEF_MOD("vin0",			811,	R8A77965_CLK_S0D2),
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 	DEF_MOD("etheravb",		812,	R8A77965_CLK_S0D6),
212
+	DEF_MOD("sata0",		815,	R8A77965_CLK_S3D2),
195
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 	DEF_MOD("imr1",			822,	R8A77965_CLK_S0D2),
196
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 	DEF_MOD("imr0",			823,	R8A77965_CLK_S0D2),
197
215
 
..
..
@@ -206,6 +224,7 @@
206
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 	DEF_MOD("can-fd",		914,	R8A77965_CLK_S3D2),
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 	DEF_MOD("can-if1",		915,	R8A77965_CLK_S3D4),
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 	DEF_MOD("can-if0",		916,	R8A77965_CLK_S3D4),
227
+	DEF_MOD("rpc-if",		917,	R8A77965_CLK_RPCD2),
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 	DEF_MOD("i2c6",			918,	R8A77965_CLK_S0D6),
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 	DEF_MOD("i2c5",			919,	R8A77965_CLK_S0D6),
211
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 	DEF_MOD("i2c-dvfs",		926,	R8A77965_CLK_CP),
..
..
@@ -244,6 +263,7 @@
244
263
 };
245
264
 
246
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 static const unsigned int r8a77965_crit_mod_clks[] __initconst = {
266
+	MOD_CLK_ID(402),	/* RWDT */
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 	MOD_CLK_ID(408),	/* INTC-AP (GIC) */
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 };
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..
..
@@ -252,25 +272,25 @@
252
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  */
253
273
 
254
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 /*
255
- *   MD		EXTAL		PLL0	PLL1	PLL3	PLL4
275
+ *   MD		EXTAL		PLL0	PLL1	PLL3	PLL4	OSC
256
276
  * 14 13 19 17	(MHz)
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- *-----------------------------------------------------------
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- * 0  0  0  0	16.66 x 1	x180	x192	x192	x144
259
- * 0  0  0  1	16.66 x 1	x180	x192	x128	x144
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+ *-----------------------------------------------------------------
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+ * 0  0  0  0	16.66 x 1	x180	x192	x192	x144	/16
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+ * 0  0  0  1	16.66 x 1	x180	x192	x128	x144	/16
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280
  * 0  0  1  0	Prohibited setting
261
- * 0  0  1  1	16.66 x 1	x180	x192	x192	x144
262
- * 0  1  0  0	20    x 1	x150	x160	x160	x120
263
- * 0  1  0  1	20    x 1	x150	x160	x106	x120
281
+ * 0  0  1  1	16.66 x 1	x180	x192	x192	x144	/16
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+ * 0  1  0  0	20    x 1	x150	x160	x160	x120	/19
283
+ * 0  1  0  1	20    x 1	x150	x160	x106	x120	/19
264
284
  * 0  1  1  0	Prohibited setting
265
- * 0  1  1  1	20    x 1	x150	x160	x160	x120
266
- * 1  0  0  0	25    x 1	x120	x128	x128	x96
267
- * 1  0  0  1	25    x 1	x120	x128	x84	x96
285
+ * 0  1  1  1	20    x 1	x150	x160	x160	x120	/19
286
+ * 1  0  0  0	25    x 1	x120	x128	x128	x96	/24
287
+ * 1  0  0  1	25    x 1	x120	x128	x84	x96	/24
268
288
  * 1  0  1  0	Prohibited setting
269
- * 1  0  1  1	25    x 1	x120	x128	x128	x96
270
- * 1  1  0  0	33.33 / 2	x180	x192	x192	x144
271
- * 1  1  0  1	33.33 / 2	x180	x192	x128	x144
289
+ * 1  0  1  1	25    x 1	x120	x128	x128	x96	/24
290
+ * 1  1  0  0	33.33 / 2	x180	x192	x192	x144	/32
291
+ * 1  1  0  1	33.33 / 2	x180	x192	x128	x144	/32
272
292
  * 1  1  1  0	Prohibited setting
273
- * 1  1  1  1	33.33 / 2	x180	x192	x192	x144
293
+ * 1  1  1  1	33.33 / 2	x180	x192	x192	x144	/32
274
294
  */
275
295
 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 11) | \
276
296
 					 (((md) & BIT(13)) >> 11) | \
..
..
@@ -278,23 +298,23 @@
278
298
 					 (((md) & BIT(17)) >> 17))
279
299
 
280
300
 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
281
-	/* EXTAL div	PLL1 mult/div	PLL3 mult/div */
282
-	{ 1,		192,	1,	192,	1,	},
283
-	{ 1,		192,	1,	128,	1,	},
284
-	{ 0, /* Prohibited setting */			},
285
-	{ 1,		192,	1,	192,	1,	},
286
-	{ 1,		160,	1,	160,	1,	},
287
-	{ 1,		160,	1,	106,	1,	},
288
-	{ 0, /* Prohibited setting */			},
289
-	{ 1,		160,	1,	160,	1,	},
290
-	{ 1,		128,	1,	128,	1,	},
291
-	{ 1,		128,	1,	84,	1,	},
292
-	{ 0, /* Prohibited setting */			},
293
-	{ 1,		128,	1,	128,	1,	},
294
-	{ 2,		192,	1,	192,	1,	},
295
-	{ 2,		192,	1,	128,	1,	},
296
-	{ 0, /* Prohibited setting */			},
297
-	{ 2,		192,	1,	192,	1,	},
301
+	/* EXTAL div	PLL1 mult/div	PLL3 mult/div	OSC prediv */
302
+	{ 1,		192,	1,	192,	1,	16,	},
303
+	{ 1,		192,	1,	128,	1,	16,	},
304
+	{ 0, /* Prohibited setting */				},
305
+	{ 1,		192,	1,	192,	1,	16,	},
306
+	{ 1,		160,	1,	160,	1,	19,	},
307
+	{ 1,		160,	1,	106,	1,	19,	},
308
+	{ 0, /* Prohibited setting */				},
309
+	{ 1,		160,	1,	160,	1,	19,	},
310
+	{ 1,		128,	1,	128,	1,	24,	},
311
+	{ 1,		128,	1,	84,	1,	24,	},
312
+	{ 0, /* Prohibited setting */				},
313
+	{ 1,		128,	1,	128,	1,	24,	},
314
+	{ 2,		192,	1,	192,	1,	32,	},
315
+	{ 2,		192,	1,	128,	1,	32,	},
316
+	{ 0, /* Prohibited setting */				},
317
+	{ 2,		192,	1,	192,	1,	32,	},
298
318
 };
299
319
 
300
320
 static int __init r8a77965_cpg_mssr_init(struct device *dev)
..
..
@@ -314,7 +334,7 @@
314
334
 	}
315
335
 
316
336
 	return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
317
-};
337
+}
318
338
 
319
339
 const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {
320
340
 	/* Core Clocks */