hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/clk/renesas/r8a7796-cpg-mssr.c
....@@ -1,21 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
2
- * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
3
+ * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
4
+ * Reset
35 *
4
- * Copyright (C) 2016 Glider bvba
6
+ * Copyright (C) 2016-2019 Glider bvba
7
+ * Copyright (C) 2018-2019 Renesas Electronics Corp.
58 *
69 * Based on r8a7795-cpg-mssr.c
710 *
811 * Copyright (C) 2015 Glider bvba
912 * Copyright (C) 2015 Renesas Electronics Corp.
10
- *
11
- * This program is free software; you can redistribute it and/or modify
12
- * it under the terms of the GNU General Public License as published by
13
- * the Free Software Foundation; version 2 of the License.
1413 */
1514
1615 #include <linux/device.h>
1716 #include <linux/init.h>
1817 #include <linux/kernel.h>
18
+#include <linux/of.h>
1919 #include <linux/soc/renesas/rcar-rst.h>
2020
2121 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
....@@ -46,6 +46,7 @@
4646 CLK_S3,
4747 CLK_SDSRC,
4848 CLK_SSPSRC,
49
+ CLK_RPCSRC,
4950 CLK_RINT,
5051
5152 /* Module Clocks */
....@@ -72,10 +73,18 @@
7273 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
7374 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
7475 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
76
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
77
+
78
+ DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
79
+ CLK_RPCSRC),
80
+ DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
81
+ R8A7796_CLK_RPC),
82
+
83
+ DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
7584
7685 /* Core Clock Outputs */
77
- DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
78
- DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
86
+ DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
87
+ DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
7988 DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
8089 DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
8190 DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
....@@ -103,20 +112,21 @@
103112 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
104113
105114 DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
115
+ DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
106116 DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
117
+ DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
107118
108119 DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
109120 DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
110121 DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014),
111122 DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
112123
113
- DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
114
- DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
124
+ DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8),
115125
116126 DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
117127 };
118128
119
-static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
129
+static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
120130 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
121131 DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
122132 DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
....@@ -127,13 +137,15 @@
127137 DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
128138 DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
129139 DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
130
- DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
131
- DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
140
+ DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
141
+ DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
132142 DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
143
+ DEF_MOD("sceg-pub", 229, R8A7796_CLK_CR),
133144 DEF_MOD("cmt3", 300, R8A7796_CLK_R),
134145 DEF_MOD("cmt2", 301, R8A7796_CLK_R),
135146 DEF_MOD("cmt1", 302, R8A7796_CLK_R),
136147 DEF_MOD("cmt0", 303, R8A7796_CLK_R),
148
+ DEF_MOD("tpu0", 304, R8A7796_CLK_S3D4),
137149 DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
138150 DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
139151 DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
....@@ -147,16 +159,16 @@
147159 DEF_MOD("rwdt", 402, R8A7796_CLK_R),
148160 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
149161 DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
150
- DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
151
- DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
152
- DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
153
- DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
154
- DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
155
- DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
156
- DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
157
- DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
158
- DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
159
- DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
162
+ DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
163
+ DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
164
+ DEF_MOD("drif31", 508, R8A7796_CLK_S3D2),
165
+ DEF_MOD("drif30", 509, R8A7796_CLK_S3D2),
166
+ DEF_MOD("drif21", 510, R8A7796_CLK_S3D2),
167
+ DEF_MOD("drif20", 511, R8A7796_CLK_S3D2),
168
+ DEF_MOD("drif11", 512, R8A7796_CLK_S3D2),
169
+ DEF_MOD("drif10", 513, R8A7796_CLK_S3D2),
170
+ DEF_MOD("drif01", 514, R8A7796_CLK_S3D2),
171
+ DEF_MOD("drif00", 515, R8A7796_CLK_S3D2),
160172 DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
161173 DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
162174 DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
....@@ -177,9 +189,12 @@
177189 DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
178190 DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
179191 DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
180
- DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
181
- DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
182
- DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
192
+ DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
193
+ DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
194
+ DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
195
+ DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1),
196
+ DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1),
197
+ DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1),
183198 DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
184199 DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
185200 DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
....@@ -209,6 +224,7 @@
209224 DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
210225 DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
211226 DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
227
+ DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2),
212228 DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
213229 DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
214230 DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
....@@ -246,34 +262,34 @@
246262 };
247263
248264 static const unsigned int r8a7796_crit_mod_clks[] __initconst = {
265
+ MOD_CLK_ID(402), /* RWDT */
249266 MOD_CLK_ID(408), /* INTC-AP (GIC) */
250267 };
251
-
252268
253269 /*
254270 * CPG Clock Data
255271 */
256272
257273 /*
258
- * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4
274
+ * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
259275 * 14 13 19 17 (MHz)
260
- *-------------------------------------------------------------------
261
- * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144
262
- * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144
276
+ *-------------------------------------------------------------------------
277
+ * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16
278
+ * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16
263279 * 0 0 1 0 Prohibited setting
264
- * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144
265
- * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120
266
- * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120
280
+ * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16
281
+ * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19
282
+ * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19
267283 * 0 1 1 0 Prohibited setting
268
- * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120
269
- * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96
270
- * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96
284
+ * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19
285
+ * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24
286
+ * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24
271287 * 1 0 1 0 Prohibited setting
272
- * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96
273
- * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144
274
- * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144
288
+ * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24
289
+ * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32
290
+ * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32
275291 * 1 1 1 0 Prohibited setting
276
- * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144
292
+ * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32
277293 */
278294 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
279295 (((md) & BIT(13)) >> 11) | \
....@@ -281,23 +297,31 @@
281297 (((md) & BIT(17)) >> 17))
282298
283299 static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
284
- /* EXTAL div PLL1 mult/div PLL3 mult/div */
285
- { 1, 192, 1, 192, 1, },
286
- { 1, 192, 1, 128, 1, },
287
- { 0, /* Prohibited setting */ },
288
- { 1, 192, 1, 192, 1, },
289
- { 1, 160, 1, 160, 1, },
290
- { 1, 160, 1, 106, 1, },
291
- { 0, /* Prohibited setting */ },
292
- { 1, 160, 1, 160, 1, },
293
- { 1, 128, 1, 128, 1, },
294
- { 1, 128, 1, 84, 1, },
295
- { 0, /* Prohibited setting */ },
296
- { 1, 128, 1, 128, 1, },
297
- { 2, 192, 1, 192, 1, },
298
- { 2, 192, 1, 128, 1, },
299
- { 0, /* Prohibited setting */ },
300
- { 2, 192, 1, 192, 1, },
300
+ /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
301
+ { 1, 192, 1, 192, 1, 16, },
302
+ { 1, 192, 1, 128, 1, 16, },
303
+ { 0, /* Prohibited setting */ },
304
+ { 1, 192, 1, 192, 1, 16, },
305
+ { 1, 160, 1, 160, 1, 19, },
306
+ { 1, 160, 1, 106, 1, 19, },
307
+ { 0, /* Prohibited setting */ },
308
+ { 1, 160, 1, 160, 1, 19, },
309
+ { 1, 128, 1, 128, 1, 24, },
310
+ { 1, 128, 1, 84, 1, 24, },
311
+ { 0, /* Prohibited setting */ },
312
+ { 1, 128, 1, 128, 1, 24, },
313
+ { 2, 192, 1, 192, 1, 32, },
314
+ { 2, 192, 1, 128, 1, 32, },
315
+ { 0, /* Prohibited setting */ },
316
+ { 2, 192, 1, 192, 1, 32, },
317
+};
318
+
319
+ /*
320
+ * Fixups for R-Car M3-W+
321
+ */
322
+
323
+static const unsigned int r8a77961_mod_nullify[] __initconst = {
324
+ MOD_CLK_ID(617), /* FCPCI0 */
301325 };
302326
303327 static int __init r8a7796_cpg_mssr_init(struct device *dev)
....@@ -316,6 +340,12 @@
316340 return -EINVAL;
317341 }
318342
343
+ if (of_device_is_compatible(dev->of_node, "renesas,r8a77961-cpg-mssr"))
344
+ mssr_mod_nullify(r8a7796_mod_clks,
345
+ ARRAY_SIZE(r8a7796_mod_clks),
346
+ r8a77961_mod_nullify,
347
+ ARRAY_SIZE(r8a77961_mod_nullify));
348
+
319349 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
320350 }
321351