.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
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1 | 2 | /* |
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2 | | - * r8a7796 Clock Pulse Generator / Module Standby and Software Reset |
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| 3 | + * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software |
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| 4 | + * Reset |
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3 | 5 | * |
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4 | | - * Copyright (C) 2016 Glider bvba |
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| 6 | + * Copyright (C) 2016-2019 Glider bvba |
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| 7 | + * Copyright (C) 2018-2019 Renesas Electronics Corp. |
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5 | 8 | * |
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6 | 9 | * Based on r8a7795-cpg-mssr.c |
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7 | 10 | * |
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8 | 11 | * Copyright (C) 2015 Glider bvba |
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9 | 12 | * Copyright (C) 2015 Renesas Electronics Corp. |
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10 | | - * |
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11 | | - * This program is free software; you can redistribute it and/or modify |
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12 | | - * it under the terms of the GNU General Public License as published by |
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13 | | - * the Free Software Foundation; version 2 of the License. |
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14 | 13 | */ |
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15 | 14 | |
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16 | 15 | #include <linux/device.h> |
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17 | 16 | #include <linux/init.h> |
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18 | 17 | #include <linux/kernel.h> |
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| 18 | +#include <linux/of.h> |
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19 | 19 | #include <linux/soc/renesas/rcar-rst.h> |
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20 | 20 | |
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21 | 21 | #include <dt-bindings/clock/r8a7796-cpg-mssr.h> |
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.. | .. |
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46 | 46 | CLK_S3, |
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47 | 47 | CLK_SDSRC, |
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48 | 48 | CLK_SSPSRC, |
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| 49 | + CLK_RPCSRC, |
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49 | 50 | CLK_RINT, |
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50 | 51 | |
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51 | 52 | /* Module Clocks */ |
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.. | .. |
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72 | 73 | DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), |
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73 | 74 | DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), |
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74 | 75 | DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), |
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| 76 | + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), |
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| 77 | + |
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| 78 | + DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, |
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| 79 | + CLK_RPCSRC), |
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| 80 | + DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, |
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| 81 | + R8A7796_CLK_RPC), |
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| 82 | + |
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| 83 | + DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), |
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75 | 84 | |
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76 | 85 | /* Core Clock Outputs */ |
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77 | | - DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), |
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78 | | - DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), |
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| 86 | + DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), |
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| 87 | + DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), |
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79 | 88 | DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), |
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80 | 89 | DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), |
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81 | 90 | DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), |
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.. | .. |
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103 | 112 | DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), |
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104 | 113 | |
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105 | 114 | DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
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| 115 | + DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1), |
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106 | 116 | DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), |
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| 117 | + DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1), |
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107 | 118 | |
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108 | 119 | DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), |
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109 | 120 | DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), |
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110 | 121 | DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014), |
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111 | 122 | DEF_DIV6P1("hdmi", R8A7796_CLK_HDMI, CLK_PLL1_DIV4, 0x250), |
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112 | 123 | |
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113 | | - DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), |
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114 | | - DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), |
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| 124 | + DEF_GEN3_OSC("osc", R8A7796_CLK_OSC, CLK_EXTAL, 8), |
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115 | 125 | |
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116 | 126 | DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), |
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117 | 127 | }; |
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118 | 128 | |
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119 | | -static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { |
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| 129 | +static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { |
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120 | 130 | DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1), |
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121 | 131 | DEF_MOD("scif5", 202, R8A7796_CLK_S3D4), |
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122 | 132 | DEF_MOD("scif4", 203, R8A7796_CLK_S3D4), |
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.. | .. |
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127 | 137 | DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), |
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128 | 138 | DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), |
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129 | 139 | DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), |
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130 | | - DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), |
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131 | | - DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), |
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| 140 | + DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1), |
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| 141 | + DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1), |
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132 | 142 | DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), |
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| 143 | + DEF_MOD("sceg-pub", 229, R8A7796_CLK_CR), |
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133 | 144 | DEF_MOD("cmt3", 300, R8A7796_CLK_R), |
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134 | 145 | DEF_MOD("cmt2", 301, R8A7796_CLK_R), |
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135 | 146 | DEF_MOD("cmt1", 302, R8A7796_CLK_R), |
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136 | 147 | DEF_MOD("cmt0", 303, R8A7796_CLK_R), |
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| 148 | + DEF_MOD("tpu0", 304, R8A7796_CLK_S3D4), |
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137 | 149 | DEF_MOD("scif2", 310, R8A7796_CLK_S3D4), |
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138 | 150 | DEF_MOD("sdif3", 311, R8A7796_CLK_SD3), |
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139 | 151 | DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), |
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.. | .. |
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147 | 159 | DEF_MOD("rwdt", 402, R8A7796_CLK_R), |
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148 | 160 | DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), |
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149 | 161 | DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3), |
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150 | | - DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), |
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151 | | - DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), |
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152 | | - DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), |
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153 | | - DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), |
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154 | | - DEF_MOD("drif5", 510, R8A7796_CLK_S3D2), |
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155 | | - DEF_MOD("drif4", 511, R8A7796_CLK_S3D2), |
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156 | | - DEF_MOD("drif3", 512, R8A7796_CLK_S3D2), |
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157 | | - DEF_MOD("drif2", 513, R8A7796_CLK_S3D2), |
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158 | | - DEF_MOD("drif1", 514, R8A7796_CLK_S3D2), |
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159 | | - DEF_MOD("drif0", 515, R8A7796_CLK_S3D2), |
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| 162 | + DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2), |
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| 163 | + DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2), |
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| 164 | + DEF_MOD("drif31", 508, R8A7796_CLK_S3D2), |
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| 165 | + DEF_MOD("drif30", 509, R8A7796_CLK_S3D2), |
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| 166 | + DEF_MOD("drif21", 510, R8A7796_CLK_S3D2), |
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| 167 | + DEF_MOD("drif20", 511, R8A7796_CLK_S3D2), |
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| 168 | + DEF_MOD("drif11", 512, R8A7796_CLK_S3D2), |
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| 169 | + DEF_MOD("drif10", 513, R8A7796_CLK_S3D2), |
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| 170 | + DEF_MOD("drif01", 514, R8A7796_CLK_S3D2), |
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| 171 | + DEF_MOD("drif00", 515, R8A7796_CLK_S3D2), |
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160 | 172 | DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1), |
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161 | 173 | DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1), |
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162 | 174 | DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1), |
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.. | .. |
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177 | 189 | DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2), |
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178 | 190 | DEF_MOD("vspb", 626, R8A7796_CLK_S0D1), |
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179 | 191 | DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1), |
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180 | | - DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4), |
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181 | | - DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4), |
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182 | | - DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4), |
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| 192 | + DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2), |
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| 193 | + DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2), |
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| 194 | + DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2), |
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| 195 | + DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1), |
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| 196 | + DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1), |
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| 197 | + DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1), |
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183 | 198 | DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), |
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184 | 199 | DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), |
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185 | 200 | DEF_MOD("du2", 722, R8A7796_CLK_S2D1), |
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.. | .. |
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209 | 224 | DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2), |
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210 | 225 | DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4), |
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211 | 226 | DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4), |
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| 227 | + DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2), |
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212 | 228 | DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6), |
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213 | 229 | DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6), |
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214 | 230 | DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP), |
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.. | .. |
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246 | 262 | }; |
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247 | 263 | |
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248 | 264 | static const unsigned int r8a7796_crit_mod_clks[] __initconst = { |
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| 265 | + MOD_CLK_ID(402), /* RWDT */ |
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249 | 266 | MOD_CLK_ID(408), /* INTC-AP (GIC) */ |
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250 | 267 | }; |
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251 | | - |
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252 | 268 | |
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253 | 269 | /* |
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254 | 270 | * CPG Clock Data |
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255 | 271 | */ |
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256 | 272 | |
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257 | 273 | /* |
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258 | | - * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 |
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| 274 | + * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC |
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259 | 275 | * 14 13 19 17 (MHz) |
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260 | | - *------------------------------------------------------------------- |
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261 | | - * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 |
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262 | | - * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 |
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| 276 | + *------------------------------------------------------------------------- |
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| 277 | + * 0 0 0 0 16.66 x 1 x180 x192 x144 x192 x144 /16 |
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| 278 | + * 0 0 0 1 16.66 x 1 x180 x192 x144 x128 x144 /16 |
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263 | 279 | * 0 0 1 0 Prohibited setting |
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264 | | - * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 |
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265 | | - * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 |
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266 | | - * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 |
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| 280 | + * 0 0 1 1 16.66 x 1 x180 x192 x144 x192 x144 /16 |
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| 281 | + * 0 1 0 0 20 x 1 x150 x160 x120 x160 x120 /19 |
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| 282 | + * 0 1 0 1 20 x 1 x150 x160 x120 x106 x120 /19 |
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267 | 283 | * 0 1 1 0 Prohibited setting |
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268 | | - * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 |
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269 | | - * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 |
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270 | | - * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 |
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| 284 | + * 0 1 1 1 20 x 1 x150 x160 x120 x160 x120 /19 |
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| 285 | + * 1 0 0 0 25 x 1 x120 x128 x96 x128 x96 /24 |
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| 286 | + * 1 0 0 1 25 x 1 x120 x128 x96 x84 x96 /24 |
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271 | 287 | * 1 0 1 0 Prohibited setting |
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272 | | - * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 |
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273 | | - * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 |
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274 | | - * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 |
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| 288 | + * 1 0 1 1 25 x 1 x120 x128 x96 x128 x96 /24 |
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| 289 | + * 1 1 0 0 33.33 / 2 x180 x192 x144 x192 x144 /32 |
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| 290 | + * 1 1 0 1 33.33 / 2 x180 x192 x144 x128 x144 /32 |
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275 | 291 | * 1 1 1 0 Prohibited setting |
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276 | | - * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 |
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| 292 | + * 1 1 1 1 33.33 / 2 x180 x192 x144 x192 x144 /32 |
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277 | 293 | */ |
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278 | 294 | #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ |
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279 | 295 | (((md) & BIT(13)) >> 11) | \ |
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.. | .. |
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281 | 297 | (((md) & BIT(17)) >> 17)) |
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282 | 298 | |
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283 | 299 | static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { |
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284 | | - /* EXTAL div PLL1 mult/div PLL3 mult/div */ |
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285 | | - { 1, 192, 1, 192, 1, }, |
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286 | | - { 1, 192, 1, 128, 1, }, |
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287 | | - { 0, /* Prohibited setting */ }, |
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288 | | - { 1, 192, 1, 192, 1, }, |
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289 | | - { 1, 160, 1, 160, 1, }, |
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290 | | - { 1, 160, 1, 106, 1, }, |
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291 | | - { 0, /* Prohibited setting */ }, |
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292 | | - { 1, 160, 1, 160, 1, }, |
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293 | | - { 1, 128, 1, 128, 1, }, |
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294 | | - { 1, 128, 1, 84, 1, }, |
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295 | | - { 0, /* Prohibited setting */ }, |
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296 | | - { 1, 128, 1, 128, 1, }, |
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297 | | - { 2, 192, 1, 192, 1, }, |
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298 | | - { 2, 192, 1, 128, 1, }, |
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299 | | - { 0, /* Prohibited setting */ }, |
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300 | | - { 2, 192, 1, 192, 1, }, |
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| 300 | + /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ |
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| 301 | + { 1, 192, 1, 192, 1, 16, }, |
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| 302 | + { 1, 192, 1, 128, 1, 16, }, |
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| 303 | + { 0, /* Prohibited setting */ }, |
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| 304 | + { 1, 192, 1, 192, 1, 16, }, |
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| 305 | + { 1, 160, 1, 160, 1, 19, }, |
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| 306 | + { 1, 160, 1, 106, 1, 19, }, |
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| 307 | + { 0, /* Prohibited setting */ }, |
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| 308 | + { 1, 160, 1, 160, 1, 19, }, |
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| 309 | + { 1, 128, 1, 128, 1, 24, }, |
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| 310 | + { 1, 128, 1, 84, 1, 24, }, |
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| 311 | + { 0, /* Prohibited setting */ }, |
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| 312 | + { 1, 128, 1, 128, 1, 24, }, |
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| 313 | + { 2, 192, 1, 192, 1, 32, }, |
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| 314 | + { 2, 192, 1, 128, 1, 32, }, |
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| 315 | + { 0, /* Prohibited setting */ }, |
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| 316 | + { 2, 192, 1, 192, 1, 32, }, |
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| 317 | +}; |
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| 318 | + |
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| 319 | + /* |
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| 320 | + * Fixups for R-Car M3-W+ |
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| 321 | + */ |
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| 322 | + |
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| 323 | +static const unsigned int r8a77961_mod_nullify[] __initconst = { |
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| 324 | + MOD_CLK_ID(617), /* FCPCI0 */ |
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301 | 325 | }; |
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302 | 326 | |
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303 | 327 | static int __init r8a7796_cpg_mssr_init(struct device *dev) |
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.. | .. |
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316 | 340 | return -EINVAL; |
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317 | 341 | } |
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318 | 342 | |
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| 343 | + if (of_device_is_compatible(dev->of_node, "renesas,r8a77961-cpg-mssr")) |
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| 344 | + mssr_mod_nullify(r8a7796_mod_clks, |
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| 345 | + ARRAY_SIZE(r8a7796_mod_clks), |
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| 346 | + r8a77961_mod_nullify, |
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| 347 | + ARRAY_SIZE(r8a77961_mod_nullify)); |
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| 348 | + |
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319 | 349 | return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); |
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320 | 350 | } |
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321 | 351 | |
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