add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clk/renesas/r8a7743-cpg-mssr.c
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@@ -1,16 +1,14 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * r8a7743 Clock Pulse Generator / Module Standby and Software Reset
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  *
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  * Copyright (C) 2016 Cogent Embedded Inc.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published
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- * by the Free Software Foundation; of the License.
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  */
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 #include <linux/device.h>
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 #include <linux/init.h>
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 #include <linux/kernel.h>
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+#include <linux/of.h>
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 #include <linux/soc/renesas/rcar-rst.h>
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 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
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@@ -37,7 +35,7 @@
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 	MOD_CLK_BASE
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 };
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-static const struct cpg_core_clk r8a7743_core_clks[] __initconst = {
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+static struct cpg_core_clk r8a7743_core_clks[] __initdata = {
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 	/* External Clock Inputs */
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 	DEF_INPUT("extal",	CLK_EXTAL),
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 	DEF_INPUT("usb_extal",	CLK_USB_EXTAL),
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@@ -94,7 +92,7 @@
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 	DEF_MOD("tmu0",			 125,	R8A7743_CLK_CP),
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 	DEF_MOD("vsp1du1",		 127,	R8A7743_CLK_ZS),
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 	DEF_MOD("vsp1du0",		 128,	R8A7743_CLK_ZS),
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-	DEF_MOD("vsp1-sy",		 131,	R8A7743_CLK_ZS),
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+	DEF_MOD("vsps",			 131,	R8A7743_CLK_ZS),
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 	DEF_MOD("scifa2",		 202,	R8A7743_CLK_MP),
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 	DEF_MOD("scifa1",		 203,	R8A7743_CLK_MP),
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 	DEF_MOD("scifa0",		 204,	R8A7743_CLK_MP),
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@@ -238,6 +236,8 @@
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 static int __init r8a7743_cpg_mssr_init(struct device *dev)
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 {
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 	const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
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+	struct device_node *np = dev->of_node;
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+	unsigned int i;
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 	u32 cpg_mode;
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 	int error;
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@@ -247,6 +247,14 @@
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 	cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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+	if (of_device_is_compatible(np, "renesas,r8a7744-cpg-mssr")) {
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+		/* RZ/G1N uses a 1/5 divider for ZG */
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+		for (i = 0; i < ARRAY_SIZE(r8a7743_core_clks); i++)
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+			if (r8a7743_core_clks[i].id == R8A7743_CLK_ZG) {
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+				r8a7743_core_clks[i].div = 5;
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+				break;
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+			}
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+	}
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 	return rcar_gen2_cpg_init(cpg_pll_config, 2, cpg_mode);
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 }
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