add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clk/qcom/gcc-msm8960.c
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@@ -1,14 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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- *
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- * This software is licensed under the terms of the GNU General Public
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- * License version 2, as published by the Free Software Foundation, and
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- * may be copied, distributed, and modified under those terms.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include <linux/kernel.h>
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@@ -30,6 +22,7 @@
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 #include "clk-pll.h"
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 #include "clk-rcg.h"
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 #include "clk-branch.h"
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+#include "clk-hfpll.h"
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 #include "reset.h"
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 static struct clk_pll pll3 = {
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@@ -84,6 +77,164 @@
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 		.num_parents = 1,
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 		.ops = &clk_pll_vote_ops,
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 	},
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+};
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+
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+static struct hfpll_data hfpll0_data = {
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+	.mode_reg = 0x3200,
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+	.l_reg = 0x3208,
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+	.m_reg = 0x320c,
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+	.n_reg = 0x3210,
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+	.config_reg = 0x3204,
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+	.status_reg = 0x321c,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x3214,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll0 = {
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+	.d = &hfpll0_data,
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+	.clkr.hw.init = &(struct clk_init_data){
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+		.parent_names = (const char *[]){ "pxo" },
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+		.num_parents = 1,
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+		.name = "hfpll0",
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+		.ops = &clk_ops_hfpll,
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+		.flags = CLK_IGNORE_UNUSED,
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+	},
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+	.lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
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+};
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+
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+static struct hfpll_data hfpll1_8064_data = {
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+	.mode_reg = 0x3240,
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+	.l_reg = 0x3248,
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+	.m_reg = 0x324c,
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+	.n_reg = 0x3250,
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+	.config_reg = 0x3244,
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+	.status_reg = 0x325c,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x3254,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct hfpll_data hfpll1_data = {
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+	.mode_reg = 0x3300,
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+	.l_reg = 0x3308,
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+	.m_reg = 0x330c,
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+	.n_reg = 0x3310,
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+	.config_reg = 0x3304,
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+	.status_reg = 0x331c,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x3314,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll1 = {
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+	.d = &hfpll1_data,
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+	.clkr.hw.init = &(struct clk_init_data){
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+		.parent_names = (const char *[]){ "pxo" },
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+		.num_parents = 1,
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+		.name = "hfpll1",
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+		.ops = &clk_ops_hfpll,
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+		.flags = CLK_IGNORE_UNUSED,
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+	},
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+	.lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
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+};
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+
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+static struct hfpll_data hfpll2_data = {
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+	.mode_reg = 0x3280,
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+	.l_reg = 0x3288,
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+	.m_reg = 0x328c,
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+	.n_reg = 0x3290,
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+	.config_reg = 0x3284,
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+	.status_reg = 0x329c,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x3294,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll2 = {
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+	.d = &hfpll2_data,
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+	.clkr.hw.init = &(struct clk_init_data){
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+		.parent_names = (const char *[]){ "pxo" },
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+		.num_parents = 1,
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+		.name = "hfpll2",
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+		.ops = &clk_ops_hfpll,
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+		.flags = CLK_IGNORE_UNUSED,
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+	},
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+	.lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
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+};
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+
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+static struct hfpll_data hfpll3_data = {
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+	.mode_reg = 0x32c0,
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+	.l_reg = 0x32c8,
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+	.m_reg = 0x32cc,
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+	.n_reg = 0x32d0,
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+	.config_reg = 0x32c4,
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+	.status_reg = 0x32dc,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x32d4,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll3 = {
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+	.d = &hfpll3_data,
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+	.clkr.hw.init = &(struct clk_init_data){
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+		.parent_names = (const char *[]){ "pxo" },
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+		.num_parents = 1,
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+		.name = "hfpll3",
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+		.ops = &clk_ops_hfpll,
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+		.flags = CLK_IGNORE_UNUSED,
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+	},
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+	.lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
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+};
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+
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+static struct hfpll_data hfpll_l2_8064_data = {
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+	.mode_reg = 0x3300,
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+	.l_reg = 0x3308,
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+	.m_reg = 0x330c,
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+	.n_reg = 0x3310,
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+	.config_reg = 0x3304,
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+	.status_reg = 0x331c,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x3314,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct hfpll_data hfpll_l2_data = {
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+	.mode_reg = 0x3400,
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+	.l_reg = 0x3408,
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+	.m_reg = 0x340c,
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+	.n_reg = 0x3410,
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+	.config_reg = 0x3404,
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+	.status_reg = 0x341c,
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+	.config_val = 0x7845c665,
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+	.droop_reg = 0x3414,
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+	.droop_val = 0x0108c000,
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+	.min_rate = 600000000UL,
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+	.max_rate = 1800000000UL,
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+};
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+
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+static struct clk_hfpll hfpll_l2 = {
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+	.d = &hfpll_l2_data,
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+	.clkr.hw.init = &(struct clk_init_data){
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+		.parent_names = (const char *[]){ "pxo" },
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+		.num_parents = 1,
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+		.name = "hfpll_l2",
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+		.ops = &clk_ops_hfpll,
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+		.flags = CLK_IGNORE_UNUSED,
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+	},
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+	.lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
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 };
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 static struct clk_pll pll14 = {
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@@ -3107,6 +3258,9 @@
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 	[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
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 	[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
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 	[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
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+	[PLL9] = &hfpll0.clkr,
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+	[PLL10] = &hfpll1.clkr,
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+	[PLL12] = &hfpll_l2.clkr,
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 };
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 static const struct qcom_reset_map gcc_msm8960_resets[] = {
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@@ -3318,6 +3472,11 @@
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 	[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
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 	[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
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 	[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
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+	[PLL9] = &hfpll0.clkr,
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+	[PLL10] = &hfpll1.clkr,
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+	[PLL12] = &hfpll_l2.clkr,
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+	[PLL16] = &hfpll2.clkr,
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+	[PLL17] = &hfpll3.clkr,
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 };
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 static const struct qcom_reset_map gcc_apq8064_resets[] = {
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@@ -3477,6 +3636,11 @@
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 	if (ret)
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 		return ret;
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+	if (match->data == &gcc_apq8064_desc) {
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+		hfpll1.d = &hfpll1_8064_data;
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+		hfpll_l2.d = &hfpll_l2_8064_data;
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+	}
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+
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 	tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
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 					      NULL, 0);
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 	if (IS_ERR(tsens))