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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/clk/qcom/dispcc-sdm845.c
....@@ -1,8 +1,9 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
3
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
3
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
44  */
55 
6
+#include <linux/clk.h>
67 #include <linux/clk-provider.h>
78 #include <linux/module.h>
89 #include <linux/platform_device.h>
....@@ -29,6 +30,8 @@
2930 	P_DSI1_PHY_PLL_OUT_DSICLK,
3031 	P_GPLL0_OUT_MAIN,
3132 	P_GPLL0_OUT_MAIN_DIV,
33
+	P_DP_PHY_PLL_LINK_CLK,
34
+	P_DP_PHY_PLL_VCO_DIV_CLK,
3235 };
3336 
3437 static const struct parent_map disp_cc_parent_map_0[] = {
....@@ -42,6 +45,20 @@
4245 	"bi_tcxo",
4346 	"dsi0_phy_pll_out_byteclk",
4447 	"dsi1_phy_pll_out_byteclk",
48
+	"core_bi_pll_test_se",
49
+};
50
+
51
+static const struct parent_map disp_cc_parent_map_1[] = {
52
+	{ P_BI_TCXO, 0 },
53
+	{ P_DP_PHY_PLL_LINK_CLK, 1 },
54
+	{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
55
+	{ P_CORE_BI_PLL_TEST_SE, 7 },
56
+};
57
+
58
+static const char * const disp_cc_parent_names_1[] = {
59
+	"bi_tcxo",
60
+	"dp_link_clk_divsel_ten",
61
+	"dp_vco_divided_clk_src_mux",
4562 	"core_bi_pll_test_se",
4663 };
4764 
....@@ -125,6 +142,81 @@
125142 		.num_parents = 4,
126143 		.flags = CLK_SET_RATE_PARENT,
127144 		.ops = &clk_byte2_ops,
145
+	},
146
+};
147
+
148
+static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
149
+	F(19200000, P_BI_TCXO, 1, 0, 0),
150
+	{ }
151
+};
152
+
153
+static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
154
+	.cmd_rcgr = 0x219c,
155
+	.mnd_width = 0,
156
+	.hid_width = 5,
157
+	.parent_map = disp_cc_parent_map_2,
158
+	.freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
159
+	.clkr.hw.init = &(struct clk_init_data){
160
+		.name = "disp_cc_mdss_dp_aux_clk_src",
161
+		.parent_names = disp_cc_parent_names_2,
162
+		.num_parents = 2,
163
+		.flags = CLK_SET_RATE_PARENT,
164
+		.ops = &clk_rcg2_ops,
165
+	},
166
+};
167
+
168
+static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
169
+	.cmd_rcgr = 0x2154,
170
+	.mnd_width = 0,
171
+	.hid_width = 5,
172
+	.parent_map = disp_cc_parent_map_1,
173
+	.clkr.hw.init = &(struct clk_init_data){
174
+		.name = "disp_cc_mdss_dp_crypto_clk_src",
175
+		.parent_names = disp_cc_parent_names_1,
176
+		.num_parents = 4,
177
+		.ops = &clk_byte2_ops,
178
+	},
179
+};
180
+
181
+static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
182
+	.cmd_rcgr = 0x2138,
183
+	.mnd_width = 0,
184
+	.hid_width = 5,
185
+	.parent_map = disp_cc_parent_map_1,
186
+	.clkr.hw.init = &(struct clk_init_data){
187
+		.name = "disp_cc_mdss_dp_link_clk_src",
188
+		.parent_names = disp_cc_parent_names_1,
189
+		.num_parents = 4,
190
+		.flags = CLK_SET_RATE_PARENT,
191
+		.ops = &clk_byte2_ops,
192
+	},
193
+};
194
+
195
+static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
196
+	.cmd_rcgr = 0x2184,
197
+	.mnd_width = 16,
198
+	.hid_width = 5,
199
+	.parent_map = disp_cc_parent_map_1,
200
+	.clkr.hw.init = &(struct clk_init_data){
201
+		.name = "disp_cc_mdss_dp_pixel1_clk_src",
202
+		.parent_names = disp_cc_parent_names_1,
203
+		.num_parents = 4,
204
+		.flags = CLK_SET_RATE_PARENT,
205
+		.ops = &clk_dp_ops,
206
+	},
207
+};
208
+
209
+static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
210
+	.cmd_rcgr = 0x216c,
211
+	.mnd_width = 16,
212
+	.hid_width = 5,
213
+	.parent_map = disp_cc_parent_map_1,
214
+	.clkr.hw.init = &(struct clk_init_data){
215
+		.name = "disp_cc_mdss_dp_pixel_clk_src",
216
+		.parent_names = disp_cc_parent_names_1,
217
+		.num_parents = 4,
218
+		.flags = CLK_SET_RATE_PARENT,
219
+		.ops = &clk_dp_ops,
128220 	},
129221 };
130222 
....@@ -391,6 +483,114 @@
391483 	},
392484 };
393485 
486
+static struct clk_branch disp_cc_mdss_dp_aux_clk = {
487
+	.halt_reg = 0x2054,
488
+	.halt_check = BRANCH_HALT,
489
+	.clkr = {
490
+		.enable_reg = 0x2054,
491
+		.enable_mask = BIT(0),
492
+		.hw.init = &(struct clk_init_data){
493
+			.name = "disp_cc_mdss_dp_aux_clk",
494
+			.parent_names = (const char *[]){
495
+				"disp_cc_mdss_dp_aux_clk_src",
496
+			},
497
+			.num_parents = 1,
498
+			.flags = CLK_SET_RATE_PARENT,
499
+			.ops = &clk_branch2_ops,
500
+		},
501
+	},
502
+};
503
+
504
+static struct clk_branch disp_cc_mdss_dp_crypto_clk = {
505
+	.halt_reg = 0x2048,
506
+	.halt_check = BRANCH_HALT,
507
+	.clkr = {
508
+		.enable_reg = 0x2048,
509
+		.enable_mask = BIT(0),
510
+		.hw.init = &(struct clk_init_data){
511
+			.name = "disp_cc_mdss_dp_crypto_clk",
512
+			.parent_names = (const char *[]){
513
+				"disp_cc_mdss_dp_crypto_clk_src",
514
+			},
515
+			.num_parents = 1,
516
+			.flags = CLK_SET_RATE_PARENT,
517
+			.ops = &clk_branch2_ops,
518
+		},
519
+	},
520
+};
521
+
522
+static struct clk_branch disp_cc_mdss_dp_link_clk = {
523
+	.halt_reg = 0x2040,
524
+	.halt_check = BRANCH_HALT,
525
+	.clkr = {
526
+		.enable_reg = 0x2040,
527
+		.enable_mask = BIT(0),
528
+		.hw.init = &(struct clk_init_data){
529
+			.name = "disp_cc_mdss_dp_link_clk",
530
+			.parent_names = (const char *[]){
531
+				"disp_cc_mdss_dp_link_clk_src",
532
+			},
533
+			.num_parents = 1,
534
+			.flags = CLK_SET_RATE_PARENT,
535
+			.ops = &clk_branch2_ops,
536
+		},
537
+	},
538
+};
539
+
540
+/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
541
+static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
542
+	.halt_reg = 0x2044,
543
+	.halt_check = BRANCH_HALT,
544
+	.clkr = {
545
+		.enable_reg = 0x2044,
546
+		.enable_mask = BIT(0),
547
+		.hw.init = &(struct clk_init_data){
548
+			.name = "disp_cc_mdss_dp_link_intf_clk",
549
+			.parent_names = (const char *[]){
550
+				"disp_cc_mdss_dp_link_clk_src",
551
+			},
552
+			.num_parents = 1,
553
+			.ops = &clk_branch2_ops,
554
+		},
555
+	},
556
+};
557
+
558
+static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
559
+	.halt_reg = 0x2050,
560
+	.halt_check = BRANCH_HALT,
561
+	.clkr = {
562
+		.enable_reg = 0x2050,
563
+		.enable_mask = BIT(0),
564
+		.hw.init = &(struct clk_init_data){
565
+			.name = "disp_cc_mdss_dp_pixel1_clk",
566
+			.parent_names = (const char *[]){
567
+				"disp_cc_mdss_dp_pixel1_clk_src",
568
+			},
569
+			.num_parents = 1,
570
+			.flags = CLK_SET_RATE_PARENT,
571
+			.ops = &clk_branch2_ops,
572
+		},
573
+	},
574
+};
575
+
576
+static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
577
+	.halt_reg = 0x204c,
578
+	.halt_check = BRANCH_HALT,
579
+	.clkr = {
580
+		.enable_reg = 0x204c,
581
+		.enable_mask = BIT(0),
582
+		.hw.init = &(struct clk_init_data){
583
+			.name = "disp_cc_mdss_dp_pixel_clk",
584
+			.parent_names = (const char *[]){
585
+				"disp_cc_mdss_dp_pixel_clk_src",
586
+			},
587
+			.num_parents = 1,
588
+			.flags = CLK_SET_RATE_PARENT,
589
+			.ops = &clk_branch2_ops,
590
+		},
591
+	},
592
+};
593
+
394594 static struct clk_branch disp_cc_mdss_esc0_clk = {
395595 	.halt_reg = 0x2038,
396596 	.halt_check = BRANCH_HALT,
....@@ -589,6 +789,19 @@
589789 	[DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
590790 	[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] =
591791 					&disp_cc_mdss_byte1_div_clk_src.clkr,
792
+	[DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
793
+	[DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
794
+	[DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr,
795
+	[DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] =
796
+					&disp_cc_mdss_dp_crypto_clk_src.clkr,
797
+	[DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
798
+	[DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
799
+	[DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
800
+	[DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
801
+	[DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] =
802
+					&disp_cc_mdss_dp_pixel1_clk_src.clkr,
803
+	[DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
804
+	[DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
592805 	[DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
593806 	[DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
594807 	[DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
....@@ -666,6 +879,7 @@
666879 	.driver		= {
667880 		.name	= "disp_cc-sdm845",
668881 		.of_match_table = disp_cc_sdm845_match_table,
882
+		.sync_state = clk_sync_state,
669883 	},
670884 };
671885