add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clk/mvebu/armada-xp.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0
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 /*
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  * Marvell Armada XP SoC clocks
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  *
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@@ -7,9 +8,6 @@
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  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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  * Andrew Lunn <andrew@lunn.ch>
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  *
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- * This file is licensed under the terms of the GNU General Public
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- * License version 2.  This program is licensed "as is" without any
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- * warranty of any kind, whether express or implied.
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  */
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 #include <linux/kernel.h>
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@@ -52,12 +50,6 @@
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 	return 250000000;
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 }
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-/* MV98DX3236 TCLK frequency is fixed to 200MHz */
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-static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar)
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-{
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-	return 200000000;
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-}
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-
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 static const u32 axp_cpu_freqs[] __initconst = {
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 	1000000000,
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 	1066000000,
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@@ -93,12 +85,6 @@
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 		cpu_freq = axp_cpu_freqs[cpu_freq_select];
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 	return cpu_freq;
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-}
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-
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-/* MV98DX3236 CLK frequency is fixed to 800MHz */
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-static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar)
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-{
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-	return 800000000;
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 }
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 static const int axp_nbclk_ratios[32][2] __initconst = {
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@@ -170,11 +156,6 @@
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 	.num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
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 };
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-static const struct coreclk_soc_desc mv98dx3236_coreclks = {
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-	.get_tclk_freq = mv98dx3236_get_tclk_freq,
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-	.get_cpu_freq = mv98dx3236_get_cpu_freq,
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-};
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-
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 /*
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  * Clock Gating Control
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  */
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@@ -209,15 +190,6 @@
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 	{ "xor1", NULL, 28, 0 },
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 	{ "sata1lnk", NULL, 29, 0 },
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 	{ "sata1", "sata1lnk", 30, 0 },
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-	{ }
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-};
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-
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-static const struct clk_gating_soc_desc mv98dx3236_gating_desc[] __initconst = {
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-	{ "ge1", NULL, 3, 0 },
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-	{ "ge0", NULL, 4, 0 },
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-	{ "pex00", NULL, 5, 0 },
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-	{ "sdio", NULL, 17, 0 },
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-	{ "xor0", NULL, 22, 0 },
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 	{ }
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 };
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