forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/clk/mmp/clk-of-mmp2.c
....@@ -3,6 +3,7 @@
33  *
44  * Copyright (C) 2012 Marvell
55  * Chao Xie <xiechao.mail@gmail.com>
6
+ * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
67  *
78  * This file is licensed under the terms of the GNU General Public
89  * License version 2. This program is licensed "as is" without any
....@@ -16,8 +17,10 @@
1617 #include <linux/delay.h>
1718 #include <linux/err.h>
1819 #include <linux/of_address.h>
20
+#include <linux/clk.h>
1921 
2022 #include <dt-bindings/clock/marvell,mmp2.h>
23
+#include <dt-bindings/power/marvell,mmp2.h>
2124 
2225 #include "clk.h"
2326 #include "reset.h"
....@@ -44,19 +47,50 @@
4447 #define APBC_SSP1	0x54
4548 #define APBC_SSP2	0x58
4649 #define APBC_SSP3	0x5c
50
+#define APBC_THERMAL0	0x90
51
+#define APBC_THERMAL1	0x98
52
+#define APBC_THERMAL2	0x9c
53
+#define APBC_THERMAL3	0xa0
4754 #define APMU_SDH0	0x54
4855 #define APMU_SDH1	0x58
4956 #define APMU_SDH2	0xe8
5057 #define APMU_SDH3	0xec
58
+#define APMU_SDH4	0x15c
5159 #define APMU_USB	0x5c
5260 #define APMU_DISP0	0x4c
5361 #define APMU_DISP1	0x110
5462 #define APMU_CCIC0	0x50
5563 #define APMU_CCIC1	0xf4
56
-#define MPMU_UART_PLL	0x14
64
+#define APMU_USBHSIC0	0xf8
65
+#define APMU_USBHSIC1	0xfc
66
+#define APMU_GPU	0xcc
67
+#define APMU_AUDIO	0x10c
68
+#define APMU_CAMERA	0x1fc
69
+
70
+#define MPMU_FCCR		0x8
71
+#define MPMU_POSR		0x10
72
+#define MPMU_UART_PLL		0x14
73
+#define MPMU_PLL2_CR		0x34
74
+#define MPMU_I2S0_PLL		0x40
75
+#define MPMU_I2S1_PLL		0x44
76
+#define MPMU_ACGR		0x1024
77
+/* MMP3 specific below */
78
+#define MPMU_PLL3_CR		0x50
79
+#define MPMU_PLL3_CTRL1		0x58
80
+#define MPMU_PLL1_CTRL		0x5c
81
+#define MPMU_PLL_DIFF_CTRL	0x68
82
+#define MPMU_PLL2_CTRL1		0x414
83
+
84
+enum mmp2_clk_model {
85
+	CLK_MODEL_MMP2,
86
+	CLK_MODEL_MMP3,
87
+};
5788 
5889 struct mmp2_clk_unit {
5990 	struct mmp_clk_unit unit;
91
+	enum mmp2_clk_model model;
92
+	struct genpd_onecell_data pd_data;
93
+	struct generic_pm_domain *pm_domains[MMP2_NR_POWER_DOMAINS];
6094 	void __iomem *mpmu_base;
6195 	void __iomem *apmu_base;
6296 	void __iomem *apbc_base;
....@@ -65,9 +99,21 @@
6599 static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
66100 	{MMP2_CLK_CLK32, "clk32", NULL, 0, 32768},
67101 	{MMP2_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
68
-	{MMP2_CLK_PLL1, "pll1", NULL, 0, 800000000},
69
-	{MMP2_CLK_PLL2, "pll2", NULL, 0, 960000000},
70102 	{MMP2_CLK_USB_PLL, "usb_pll", NULL, 0, 480000000},
103
+	{0, "i2s_pll", NULL, 0, 99666667},
104
+};
105
+
106
+static struct mmp_param_pll_clk pll_clks[] = {
107
+	{MMP2_CLK_PLL1,   "pll1",   797330000, MPMU_FCCR,          0x4000, MPMU_POSR,     0},
108
+	{MMP2_CLK_PLL2,   "pll2",           0, MPMU_PLL2_CR,       0x0300, MPMU_PLL2_CR, 10},
109
+};
110
+
111
+static struct mmp_param_pll_clk mmp3_pll_clks[] = {
112
+	{MMP2_CLK_PLL2,   "pll1",   797330000, MPMU_FCCR,          0x4000, MPMU_POSR,     0,      26000000, MPMU_PLL1_CTRL,      25},
113
+	{MMP2_CLK_PLL2,   "pll2",           0, MPMU_PLL2_CR,       0x0300, MPMU_PLL2_CR, 10,      26000000, MPMU_PLL2_CTRL1,     25},
114
+	{MMP3_CLK_PLL1_P, "pll1_p",         0, MPMU_PLL_DIFF_CTRL, 0x0010, 0,             0,     797330000, MPMU_PLL_DIFF_CTRL,   0},
115
+	{MMP3_CLK_PLL2_P, "pll2_p",         0, MPMU_PLL_DIFF_CTRL, 0x0100, MPMU_PLL2_CR, 10,      26000000, MPMU_PLL_DIFF_CTRL,   5},
116
+	{MMP3_CLK_PLL3,   "pll3",           0, MPMU_PLL3_CR,       0x0300, MPMU_PLL3_CR, 10,      26000000, MPMU_PLL3_CTRL1,     25},
71117 };
72118 
73119 static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
....@@ -103,13 +149,51 @@
103149 	{.num = 3521, .den = 689},	/*19.23MHZ */
104150 };
105151 
106
-static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit)
152
+static struct mmp_clk_factor_masks i2s_factor_masks = {
153
+	.factor = 2,
154
+	.num_mask = 0x7fff,
155
+	.den_mask = 0x1fff,
156
+	.num_shift = 0,
157
+	.den_shift = 15,
158
+	.enable_mask = 0xd0000000,
159
+};
160
+
161
+static struct mmp_clk_factor_tbl i2s_factor_tbl[] = {
162
+	{.num = 24868, .den =  511},	/*  2.0480 MHz */
163
+	{.num = 28003, .den =  793},	/*  2.8224 MHz */
164
+	{.num = 24941, .den = 1025},	/*  4.0960 MHz */
165
+	{.num = 28003, .den = 1586},	/*  5.6448 MHz */
166
+	{.num = 31158, .den = 2561},	/*  8.1920 MHz */
167
+	{.num = 16288, .den = 1845},	/* 11.2896 MHz */
168
+	{.num = 20772, .den = 2561},	/* 12.2880 MHz */
169
+	{.num =  8144, .den = 1845},	/* 22.5792 MHz */
170
+	{.num = 10386, .den = 2561},	/* 24.5760 MHz */
171
+};
172
+
173
+static DEFINE_SPINLOCK(acgr_lock);
174
+
175
+static struct mmp_param_gate_clk mpmu_gate_clks[] = {
176
+	{MMP2_CLK_I2S0, "i2s0_clk", "i2s0_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x200000, 0x200000, 0x0, 0, &acgr_lock},
177
+	{MMP2_CLK_I2S1, "i2s1_clk", "i2s1_pll", CLK_SET_RATE_PARENT, MPMU_ACGR, 0x100000, 0x100000, 0x0, 0, &acgr_lock},
178
+};
179
+
180
+static void mmp2_main_clk_init(struct mmp2_clk_unit *pxa_unit)
107181 {
108182 	struct clk *clk;
109183 	struct mmp_clk_unit *unit = &pxa_unit->unit;
110184 
111185 	mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
112186 					ARRAY_SIZE(fixed_rate_clks));
187
+
188
+	if (pxa_unit->model == CLK_MODEL_MMP3) {
189
+		mmp_register_pll_clks(unit, mmp3_pll_clks,
190
+					pxa_unit->mpmu_base,
191
+					ARRAY_SIZE(mmp3_pll_clks));
192
+	} else {
193
+		mmp_register_pll_clks(unit, pll_clks,
194
+					pxa_unit->mpmu_base,
195
+					ARRAY_SIZE(pll_clks));
196
+	}
113197 
114198 	mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
115199 					ARRAY_SIZE(fixed_factor_clks));
....@@ -120,21 +204,35 @@
120204 				&uart_factor_masks, uart_factor_tbl,
121205 				ARRAY_SIZE(uart_factor_tbl), NULL);
122206 	mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk);
207
+
208
+	mmp_clk_register_factor("i2s0_pll", "pll1_4",
209
+				CLK_SET_RATE_PARENT,
210
+				pxa_unit->mpmu_base + MPMU_I2S0_PLL,
211
+				&i2s_factor_masks, i2s_factor_tbl,
212
+				ARRAY_SIZE(i2s_factor_tbl), NULL);
213
+	mmp_clk_register_factor("i2s1_pll", "pll1_4",
214
+				CLK_SET_RATE_PARENT,
215
+				pxa_unit->mpmu_base + MPMU_I2S1_PLL,
216
+				&i2s_factor_masks, i2s_factor_tbl,
217
+				ARRAY_SIZE(i2s_factor_tbl), NULL);
218
+
219
+	mmp_register_gate_clks(unit, mpmu_gate_clks, pxa_unit->mpmu_base,
220
+				ARRAY_SIZE(mpmu_gate_clks));
123221 }
124222 
125223 static DEFINE_SPINLOCK(uart0_lock);
126224 static DEFINE_SPINLOCK(uart1_lock);
127225 static DEFINE_SPINLOCK(uart2_lock);
128
-static const char *uart_parent_names[] = {"uart_pll", "vctcxo"};
226
+static const char * const uart_parent_names[] = {"uart_pll", "vctcxo"};
129227 
130228 static DEFINE_SPINLOCK(ssp0_lock);
131229 static DEFINE_SPINLOCK(ssp1_lock);
132230 static DEFINE_SPINLOCK(ssp2_lock);
133231 static DEFINE_SPINLOCK(ssp3_lock);
134
-static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
232
+static const char * const ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
135233 
136234 static DEFINE_SPINLOCK(timer_lock);
137
-static const char *timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
235
+static const char * const timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"};
138236 
139237 static DEFINE_SPINLOCK(reset_lock);
140238 
....@@ -174,6 +272,13 @@
174272 	{MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock},
175273 	{MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock},
176274 	{MMP2_CLK_TIMER, "timer_clk", "timer_mux", CLK_SET_RATE_PARENT, APBC_TIMER, 0x7, 0x3, 0x0, 0, &timer_lock},
275
+	{MMP2_CLK_THERMAL0, "thermal0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL0, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
276
+};
277
+
278
+static struct mmp_param_gate_clk mmp3_apbc_gate_clks[] = {
279
+	{MMP3_CLK_THERMAL1, "thermal1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL1, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
280
+	{MMP3_CLK_THERMAL2, "thermal2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL2, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
281
+	{MMP3_CLK_THERMAL3, "thermal3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_THERMAL3, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
177282 };
178283 
179284 static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
....@@ -185,23 +290,41 @@
185290 
186291 	mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
187292 				ARRAY_SIZE(apbc_gate_clks));
293
+
294
+	if (pxa_unit->model == CLK_MODEL_MMP3) {
295
+		mmp_register_gate_clks(unit, mmp3_apbc_gate_clks, pxa_unit->apbc_base,
296
+					ARRAY_SIZE(mmp3_apbc_gate_clks));
297
+	}
188298 }
189299 
190300 static DEFINE_SPINLOCK(sdh_lock);
191
-static const char *sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
301
+static const char * const sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
192302 static struct mmp_clk_mix_config sdh_mix_config = {
193303 	.reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32),
194304 };
195305 
196306 static DEFINE_SPINLOCK(usb_lock);
307
+static DEFINE_SPINLOCK(usbhsic0_lock);
308
+static DEFINE_SPINLOCK(usbhsic1_lock);
197309 
198310 static DEFINE_SPINLOCK(disp0_lock);
199311 static DEFINE_SPINLOCK(disp1_lock);
200
-static const char *disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
312
+static const char * const disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
201313 
202314 static DEFINE_SPINLOCK(ccic0_lock);
203315 static DEFINE_SPINLOCK(ccic1_lock);
204
-static const char *ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
316
+static const char * const ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"};
317
+
318
+static DEFINE_SPINLOCK(gpu_lock);
319
+static const char * const mmp2_gpu_gc_parent_names[] =  {"pll1_2", "pll1_3", "pll2_2", "pll2_3", "pll2", "usb_pll"};
320
+static u32 mmp2_gpu_gc_parent_table[] =          { 0x0000,   0x0040,   0x0080,   0x00c0,   0x1000, 0x1040   };
321
+static const char * const mmp2_gpu_bus_parent_names[] = {"pll1_4", "pll2",   "pll2_2", "usb_pll"};
322
+static u32 mmp2_gpu_bus_parent_table[] =         { 0x0000,   0x0020,   0x0030,   0x4020   };
323
+static const char * const mmp3_gpu_bus_parent_names[] = {"pll1_4", "pll1_6", "pll1_2", "pll2_2"};
324
+static const char * const mmp3_gpu_gc_parent_names[] =  {"pll1",   "pll2",   "pll1_p", "pll2_p"};
325
+
326
+static DEFINE_SPINLOCK(audio_lock);
327
+
205328 static struct mmp_clk_mix_config ccic0_mix_config = {
206329 	.reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32),
207330 };
....@@ -214,24 +337,41 @@
214337 	{MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock},
215338 };
216339 
340
+static struct mmp_param_mux_clk mmp3_apmu_mux_clks[] = {
341
+	{0, "gpu_bus_mux", mmp3_gpu_bus_parent_names, ARRAY_SIZE(mmp3_gpu_bus_parent_names),
342
+									CLK_SET_RATE_PARENT, APMU_GPU, 4, 2, 0, &gpu_lock},
343
+	{0, "gpu_3d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
344
+									CLK_SET_RATE_PARENT, APMU_GPU, 6, 2, 0, &gpu_lock},
345
+	{0, "gpu_2d_mux", mmp3_gpu_gc_parent_names, ARRAY_SIZE(mmp3_gpu_gc_parent_names),
346
+									CLK_SET_RATE_PARENT, APMU_GPU, 12, 2, 0, &gpu_lock},
347
+};
348
+
217349 static struct mmp_param_div_clk apmu_div_clks[] = {
218
-	{0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock},
350
+	{0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, CLK_DIVIDER_ONE_BASED, &disp0_lock},
219351 	{0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock},
220
-	{0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock},
352
+	{0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, CLK_DIVIDER_ONE_BASED, &disp1_lock},
221353 	{0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
222354 	{0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
223355 };
224356 
357
+static struct mmp_param_div_clk mmp3_apmu_div_clks[] = {
358
+	{0, "gpu_3d_div", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 24, 4, 0, &gpu_lock},
359
+	{0, "gpu_2d_div", "gpu_2d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 28, 4, 0, &gpu_lock},
360
+};
361
+
225362 static struct mmp_param_gate_clk apmu_gate_clks[] = {
226363 	{MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock},
364
+	{MMP2_CLK_USBHSIC0, "usbhsic0_clk", "usb_pll", 0, APMU_USBHSIC0, 0x1b, 0x1b, 0x0, 0, &usbhsic0_lock},
365
+	{MMP2_CLK_USBHSIC1, "usbhsic1_clk", "usb_pll", 0, APMU_USBHSIC1, 0x1b, 0x1b, 0x0, 0, &usbhsic1_lock},
227366 	/* The gate clocks has mux parent. */
228367 	{MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
229368 	{MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
230369 	{MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
231370 	{MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
232
-	{MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
371
+	{MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x12, 0x12, 0x0, 0, &disp0_lock},
372
+	{MMP2_CLK_DISP0_LCDC, "disp0_lcdc_clk", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 0x09, 0x09, 0x0, 0, &disp0_lock},
233373 	{MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
234
-	{MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock},
374
+	{MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x09, 0x09, 0x0, 0, &disp1_lock},
235375 	{MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock},
236376 	{MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock},
237377 	{MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock},
....@@ -239,6 +379,18 @@
239379 	{MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
240380 	{MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
241381 	{MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
382
+	{MMP2_CLK_GPU_BUS, "gpu_bus_clk", "gpu_bus_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0xa, 0xa, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
383
+	{MMP2_CLK_AUDIO, "audio_clk", "audio_mix_clk", CLK_SET_RATE_PARENT, APMU_AUDIO, 0x12, 0x12, 0x0, 0, &audio_lock},
384
+};
385
+
386
+static struct mmp_param_gate_clk mmp2_apmu_gate_clks[] = {
387
+	{MMP2_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_mux", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
388
+};
389
+
390
+static struct mmp_param_gate_clk mmp3_apmu_gate_clks[] = {
391
+	{MMP3_CLK_SDH4, "sdh4_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH4, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
392
+	{MMP3_CLK_GPU_3D, "gpu_3d_clk", "gpu_3d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x5, 0x5, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
393
+	{MMP3_CLK_GPU_2D, "gpu_2d_clk", "gpu_2d_div", CLK_SET_RATE_PARENT, APMU_GPU, 0x1c0000, 0x1c0000, 0x0, MMP_CLK_GATE_NEED_DELAY, &gpu_lock},
242394 };
243395 
244396 static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit)
....@@ -274,6 +426,34 @@
274426 
275427 	mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
276428 				ARRAY_SIZE(apmu_gate_clks));
429
+
430
+	if (pxa_unit->model == CLK_MODEL_MMP3) {
431
+		mmp_register_mux_clks(unit, mmp3_apmu_mux_clks, pxa_unit->apmu_base,
432
+					ARRAY_SIZE(mmp3_apmu_mux_clks));
433
+
434
+		mmp_register_div_clks(unit, mmp3_apmu_div_clks, pxa_unit->apmu_base,
435
+					ARRAY_SIZE(mmp3_apmu_div_clks));
436
+
437
+		mmp_register_gate_clks(unit, mmp3_apmu_gate_clks, pxa_unit->apmu_base,
438
+					ARRAY_SIZE(mmp3_apmu_gate_clks));
439
+	} else {
440
+		clk_register_mux_table(NULL, "gpu_3d_mux", mmp2_gpu_gc_parent_names,
441
+					ARRAY_SIZE(mmp2_gpu_gc_parent_names),
442
+					CLK_SET_RATE_PARENT,
443
+					pxa_unit->apmu_base + APMU_GPU,
444
+					0, 0x10c0, 0,
445
+					mmp2_gpu_gc_parent_table, &gpu_lock);
446
+
447
+		clk_register_mux_table(NULL, "gpu_bus_mux", mmp2_gpu_bus_parent_names,
448
+					ARRAY_SIZE(mmp2_gpu_bus_parent_names),
449
+					CLK_SET_RATE_PARENT,
450
+					pxa_unit->apmu_base + APMU_GPU,
451
+					0, 0x4030, 0,
452
+					mmp2_gpu_bus_parent_table, &gpu_lock);
453
+
454
+		mmp_register_gate_clks(unit, mmp2_apmu_gate_clks, pxa_unit->apmu_base,
455
+					ARRAY_SIZE(mmp2_apmu_gate_clks));
456
+	}
277457 }
278458 
279459 static void mmp2_clk_reset_init(struct device_node *np,
....@@ -298,6 +478,41 @@
298478 	mmp_clk_reset_register(np, cells, nr_resets);
299479 }
300480 
481
+static void mmp2_pm_domain_init(struct device_node *np,
482
+				struct mmp2_clk_unit *pxa_unit)
483
+{
484
+	if (pxa_unit->model == CLK_MODEL_MMP3) {
485
+		pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]
486
+			= mmp_pm_domain_register("gpu",
487
+				pxa_unit->apmu_base + APMU_GPU,
488
+				0x0600, 0x40003, 0x18000c, 0, &gpu_lock);
489
+	} else {
490
+		pxa_unit->pm_domains[MMP2_POWER_DOMAIN_GPU]
491
+			= mmp_pm_domain_register("gpu",
492
+				pxa_unit->apmu_base + APMU_GPU,
493
+				0x8600, 0x00003, 0x00000c,
494
+				MMP_PM_DOMAIN_NO_DISABLE, &gpu_lock);
495
+	}
496
+	pxa_unit->pd_data.num_domains++;
497
+
498
+	pxa_unit->pm_domains[MMP2_POWER_DOMAIN_AUDIO]
499
+		= mmp_pm_domain_register("audio",
500
+			pxa_unit->apmu_base + APMU_AUDIO,
501
+			0x600, 0x2, 0, 0, &audio_lock);
502
+	pxa_unit->pd_data.num_domains++;
503
+
504
+	if (pxa_unit->model == CLK_MODEL_MMP3) {
505
+		pxa_unit->pm_domains[MMP3_POWER_DOMAIN_CAMERA]
506
+			= mmp_pm_domain_register("camera",
507
+				pxa_unit->apmu_base + APMU_CAMERA,
508
+				0x600, 0, 0, 0, NULL);
509
+		pxa_unit->pd_data.num_domains++;
510
+	}
511
+
512
+	pxa_unit->pd_data.domains = pxa_unit->pm_domains;
513
+	of_genpd_add_provider_onecell(np, &pxa_unit->pd_data);
514
+}
515
+
301516 static void __init mmp2_clk_init(struct device_node *np)
302517 {
303518 	struct mmp2_clk_unit *pxa_unit;
....@@ -305,6 +520,11 @@
305520 	pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
306521 	if (!pxa_unit)
307522 		return;
523
+
524
+	if (of_device_is_compatible(np, "marvell,mmp3-clock"))
525
+		pxa_unit->model = CLK_MODEL_MMP3;
526
+	else
527
+		pxa_unit->model = CLK_MODEL_MMP2;
308528 
309529 	pxa_unit->mpmu_base = of_iomap(np, 0);
310530 	if (!pxa_unit->mpmu_base) {
....@@ -324,9 +544,11 @@
324544 		goto unmap_apmu_region;
325545 	}
326546 
547
+	mmp2_pm_domain_init(np, pxa_unit);
548
+
327549 	mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS);
328550 
329
-	mmp2_pll_init(pxa_unit);
551
+	mmp2_main_clk_init(pxa_unit);
330552 
331553 	mmp2_apb_periph_clk_init(pxa_unit);
332554 
....@@ -345,3 +567,4 @@
345567 }
346568 
347569 CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init);
570
+CLK_OF_DECLARE(mmp3_clk, "marvell,mmp3-clock", mmp2_clk_init);