hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/drivers/clk/mediatek/clk-mtk.h
....@@ -1,15 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23 * Copyright (c) 2014 MediaTek Inc.
34 * Author: James Liao <jamesjj.liao@mediatek.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12
- * GNU General Public License for more details.
135 */
146
157 #ifndef __DRV_CLK_MTK_H
....@@ -81,15 +73,13 @@
8173 signed char divider_shift;
8274 signed char divider_width;
8375
76
+ u8 mux_flags;
77
+
8478 signed char num_parents;
8579 };
8680
87
-/*
88
- * In case the rate change propagation to parent clocks is undesirable,
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- * this macro allows to specify the clock flags manually.
90
- */
91
-#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
92
- _gate, _flags) { \
81
+#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \
82
+ _width, _gate, _flags, _muxflags) { \
9383 .id = _id, \
9484 .name = _name, \
9585 .mux_reg = _reg, \
....@@ -101,7 +91,17 @@
10191 .parent_names = _parents, \
10292 .num_parents = ARRAY_SIZE(_parents), \
10393 .flags = _flags, \
94
+ .mux_flags = _muxflags, \
10495 }
96
+
97
+/*
98
+ * In case the rate change propagation to parent clocks is undesirable,
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+ * this macro allows to specify the clock flags manually.
100
+ */
101
+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
102
+ _gate, _flags) \
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+ MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
104
+ _shift, _width, _gate, _flags, 0)
105105
106106 /*
107107 * Unless necessary, all MUX_GATE clocks propagate rate changes to their
....@@ -111,7 +111,11 @@
111111 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
112112 _gate, CLK_SET_RATE_PARENT)
113113
114
-#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
114
+#define MUX(_id, _name, _parents, _reg, _shift, _width) \
115
+ MUX_FLAGS(_id, _name, _parents, _reg, \
116
+ _shift, _width, CLK_SET_RATE_PARENT)
117
+
118
+#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \
115119 .id = _id, \
116120 .name = _name, \
117121 .mux_reg = _reg, \
....@@ -121,7 +125,7 @@
121125 .divider_shift = -1, \
122126 .parent_names = _parents, \
123127 .num_parents = ARRAY_SIZE(_parents), \
124
- .flags = CLK_SET_RATE_PARENT, \
128
+ .flags = _flags, \
125129 }
126130
127131 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
....@@ -158,11 +162,17 @@
158162 const struct mtk_gate_regs *regs;
159163 int shift;
160164 const struct clk_ops *ops;
165
+ unsigned long flags;
161166 };
162167
163168 int mtk_clk_register_gates(struct device_node *node,
164169 const struct mtk_gate *clks, int num,
165170 struct clk_onecell_data *clk_data);
171
+
172
+int mtk_clk_register_gates_with_dev(struct device_node *node,
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+ const struct mtk_gate *clks,
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+ int num, struct clk_onecell_data *clk_data,
175
+ struct device *dev);
166176
167177 struct mtk_clk_divider {
168178 int id;
....@@ -214,10 +224,13 @@
214224 unsigned int flags;
215225 const struct clk_ops *ops;
216226 u32 rst_bar_mask;
227
+ unsigned long fmin;
217228 unsigned long fmax;
218229 int pcwbits;
230
+ int pcwibits;
219231 uint32_t pcw_reg;
220232 int pcw_shift;
233
+ uint32_t pcw_chg_reg;
221234 const struct mtk_pll_div_table *div_table;
222235 const char *parent_name;
223236 };
....@@ -232,4 +245,7 @@
232245 void mtk_register_reset_controller(struct device_node *np,
233246 unsigned int num_regs, int regofs);
234247
248
+void mtk_register_reset_controller_set_clr(struct device_node *np,
249
+ unsigned int num_regs, int regofs);
250
+
235251 #endif /* __DRV_CLK_MTK_H */