.. | .. |
---|
| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
---|
1 | 2 | /* |
---|
2 | 3 | * Copyright (c) 2014 MediaTek Inc. |
---|
3 | 4 | * Author: James Liao <jamesjj.liao@mediatek.com> |
---|
4 | | - * |
---|
5 | | - * This program is free software; you can redistribute it and/or modify |
---|
6 | | - * it under the terms of the GNU General Public License version 2 as |
---|
7 | | - * published by the Free Software Foundation. |
---|
8 | | - * |
---|
9 | | - * This program is distributed in the hope that it will be useful, |
---|
10 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
---|
11 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
---|
12 | | - * GNU General Public License for more details. |
---|
13 | 5 | */ |
---|
14 | 6 | |
---|
15 | 7 | #ifndef __DRV_CLK_MTK_H |
---|
.. | .. |
---|
81 | 73 | signed char divider_shift; |
---|
82 | 74 | signed char divider_width; |
---|
83 | 75 | |
---|
| 76 | + u8 mux_flags; |
---|
| 77 | + |
---|
84 | 78 | signed char num_parents; |
---|
85 | 79 | }; |
---|
86 | 80 | |
---|
87 | | -/* |
---|
88 | | - * In case the rate change propagation to parent clocks is undesirable, |
---|
89 | | - * this macro allows to specify the clock flags manually. |
---|
90 | | - */ |
---|
91 | | -#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ |
---|
92 | | - _gate, _flags) { \ |
---|
| 81 | +#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ |
---|
| 82 | + _width, _gate, _flags, _muxflags) { \ |
---|
93 | 83 | .id = _id, \ |
---|
94 | 84 | .name = _name, \ |
---|
95 | 85 | .mux_reg = _reg, \ |
---|
.. | .. |
---|
101 | 91 | .parent_names = _parents, \ |
---|
102 | 92 | .num_parents = ARRAY_SIZE(_parents), \ |
---|
103 | 93 | .flags = _flags, \ |
---|
| 94 | + .mux_flags = _muxflags, \ |
---|
104 | 95 | } |
---|
| 96 | + |
---|
| 97 | +/* |
---|
| 98 | + * In case the rate change propagation to parent clocks is undesirable, |
---|
| 99 | + * this macro allows to specify the clock flags manually. |
---|
| 100 | + */ |
---|
| 101 | +#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ |
---|
| 102 | + _gate, _flags) \ |
---|
| 103 | + MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ |
---|
| 104 | + _shift, _width, _gate, _flags, 0) |
---|
105 | 105 | |
---|
106 | 106 | /* |
---|
107 | 107 | * Unless necessary, all MUX_GATE clocks propagate rate changes to their |
---|
.. | .. |
---|
111 | 111 | MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ |
---|
112 | 112 | _gate, CLK_SET_RATE_PARENT) |
---|
113 | 113 | |
---|
114 | | -#define MUX(_id, _name, _parents, _reg, _shift, _width) { \ |
---|
| 114 | +#define MUX(_id, _name, _parents, _reg, _shift, _width) \ |
---|
| 115 | + MUX_FLAGS(_id, _name, _parents, _reg, \ |
---|
| 116 | + _shift, _width, CLK_SET_RATE_PARENT) |
---|
| 117 | + |
---|
| 118 | +#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ |
---|
115 | 119 | .id = _id, \ |
---|
116 | 120 | .name = _name, \ |
---|
117 | 121 | .mux_reg = _reg, \ |
---|
.. | .. |
---|
121 | 125 | .divider_shift = -1, \ |
---|
122 | 126 | .parent_names = _parents, \ |
---|
123 | 127 | .num_parents = ARRAY_SIZE(_parents), \ |
---|
124 | | - .flags = CLK_SET_RATE_PARENT, \ |
---|
| 128 | + .flags = _flags, \ |
---|
125 | 129 | } |
---|
126 | 130 | |
---|
127 | 131 | #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ |
---|
.. | .. |
---|
158 | 162 | const struct mtk_gate_regs *regs; |
---|
159 | 163 | int shift; |
---|
160 | 164 | const struct clk_ops *ops; |
---|
| 165 | + unsigned long flags; |
---|
161 | 166 | }; |
---|
162 | 167 | |
---|
163 | 168 | int mtk_clk_register_gates(struct device_node *node, |
---|
164 | 169 | const struct mtk_gate *clks, int num, |
---|
165 | 170 | struct clk_onecell_data *clk_data); |
---|
| 171 | + |
---|
| 172 | +int mtk_clk_register_gates_with_dev(struct device_node *node, |
---|
| 173 | + const struct mtk_gate *clks, |
---|
| 174 | + int num, struct clk_onecell_data *clk_data, |
---|
| 175 | + struct device *dev); |
---|
166 | 176 | |
---|
167 | 177 | struct mtk_clk_divider { |
---|
168 | 178 | int id; |
---|
.. | .. |
---|
214 | 224 | unsigned int flags; |
---|
215 | 225 | const struct clk_ops *ops; |
---|
216 | 226 | u32 rst_bar_mask; |
---|
| 227 | + unsigned long fmin; |
---|
217 | 228 | unsigned long fmax; |
---|
218 | 229 | int pcwbits; |
---|
| 230 | + int pcwibits; |
---|
219 | 231 | uint32_t pcw_reg; |
---|
220 | 232 | int pcw_shift; |
---|
| 233 | + uint32_t pcw_chg_reg; |
---|
221 | 234 | const struct mtk_pll_div_table *div_table; |
---|
222 | 235 | const char *parent_name; |
---|
223 | 236 | }; |
---|
.. | .. |
---|
232 | 245 | void mtk_register_reset_controller(struct device_node *np, |
---|
233 | 246 | unsigned int num_regs, int regofs); |
---|
234 | 247 | |
---|
| 248 | +void mtk_register_reset_controller_set_clr(struct device_node *np, |
---|
| 249 | + unsigned int num_regs, int regofs); |
---|
| 250 | + |
---|
235 | 251 | #endif /* __DRV_CLK_MTK_H */ |
---|