add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clk/mediatek/clk-mtk.h
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@@ -1,15 +1,7 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (c) 2014 MediaTek Inc.
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  * Author: James Liao <jamesjj.liao@mediatek.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef __DRV_CLK_MTK_H
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@@ -81,15 +73,13 @@
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 	signed char divider_shift;
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 	signed char divider_width;
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+	u8 mux_flags;
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+
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 	signed char num_parents;
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 };
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-/*
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- * In case the rate change propagation to parent clocks is undesirable,
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- * this macro allows to specify the clock flags manually.
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- */
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-#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,	\
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-			_gate, _flags) {				\
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+#define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift,		\
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+				_width, _gate, _flags, _muxflags) {	\
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 		.id = _id,						\
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 		.name = _name,						\
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 		.mux_reg = _reg,					\
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@@ -101,7 +91,17 @@
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 		.parent_names = _parents,				\
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 		.num_parents = ARRAY_SIZE(_parents),			\
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 		.flags = _flags,					\
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+		.mux_flags = _muxflags,					\
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 	}
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+
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+/*
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+ * In case the rate change propagation to parent clocks is undesirable,
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+ * this macro allows to specify the clock flags manually.
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+ */
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+#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,	\
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+			_gate, _flags)					\
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+		MUX_GATE_FLAGS_2(_id, _name, _parents, _reg,		\
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+					_shift, _width, _gate, _flags, 0)
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 /*
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  * Unless necessary, all MUX_GATE clocks propagate rate changes to their
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@@ -111,7 +111,11 @@
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 	MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width,	\
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 		_gate, CLK_SET_RATE_PARENT)
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-#define MUX(_id, _name, _parents, _reg, _shift, _width) {		\
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+#define MUX(_id, _name, _parents, _reg, _shift, _width)			\
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+	MUX_FLAGS(_id, _name, _parents, _reg,				\
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+		  _shift, _width, CLK_SET_RATE_PARENT)
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+
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+#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) {	\
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 		.id = _id,						\
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 		.name = _name,						\
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 		.mux_reg = _reg,					\
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@@ -121,7 +125,7 @@
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 		.divider_shift = -1,					\
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 		.parent_names = _parents,				\
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 		.num_parents = ARRAY_SIZE(_parents),			\
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-		.flags = CLK_SET_RATE_PARENT,				\
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+		.flags = _flags,				\
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 	}
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 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg,	\
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@@ -158,11 +162,17 @@
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 	const struct mtk_gate_regs *regs;
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 	int shift;
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 	const struct clk_ops *ops;
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+	unsigned long flags;
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 };
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 int mtk_clk_register_gates(struct device_node *node,
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 			const struct mtk_gate *clks, int num,
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 			struct clk_onecell_data *clk_data);
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+
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+int mtk_clk_register_gates_with_dev(struct device_node *node,
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+		const struct mtk_gate *clks,
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+		int num, struct clk_onecell_data *clk_data,
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+		struct device *dev);
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 struct mtk_clk_divider {
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 	int id;
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@@ -214,10 +224,13 @@
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 	unsigned int flags;
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 	const struct clk_ops *ops;
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 	u32 rst_bar_mask;
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+	unsigned long fmin;
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 	unsigned long fmax;
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 	int pcwbits;
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+	int pcwibits;
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 	uint32_t pcw_reg;
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 	int pcw_shift;
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+	uint32_t pcw_chg_reg;
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 	const struct mtk_pll_div_table *div_table;
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 	const char *parent_name;
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 };
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@@ -232,4 +245,7 @@
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 void mtk_register_reset_controller(struct device_node *np,
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 			unsigned int num_regs, int regofs);
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+void mtk_register_reset_controller_set_clr(struct device_node *np,
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+	unsigned int num_regs, int regofs);
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+
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 #endif /* __DRV_CLK_MTK_H */