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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/clk/clk-qoriq.c
....@@ -1,9 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright 2013 Freescale Semiconductor, Inc.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
74  *
85  * clock driver for Freescale QorIQ SoCs.
96  */
....@@ -34,6 +31,7 @@
3431 #define CGA_PLL4	4	/* only on clockgen-1.0, which lacks CGB */
3532 #define CGB_PLL1	4
3633 #define CGB_PLL2	5
34
+#define MAX_PLL_DIV	32
3735 
3836 struct clockgen_pll_div {
3937 	struct clk *clk;
....@@ -41,7 +39,7 @@
4139 };
4240 
4341 struct clockgen_pll {
44
-	struct clockgen_pll_div div[8];
42
+	struct clockgen_pll_div div[MAX_PLL_DIV];
4543 };
4644 
4745 #define CLKSEL_VALID	1
....@@ -79,7 +77,7 @@
7977 	const struct clockgen_muxinfo *cmux_groups[2];
8078 	const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
8179 	void (*init_periph)(struct clockgen *cg);
82
-	int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
80
+	int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
8381 	u32 pll_mask;	/* 1 << n bit set if PLL n is valid */
8482 	u32 flags;	/* CG_xxx */
8583 };
....@@ -97,6 +95,7 @@
9795 };
9896 
9997 static struct clockgen clockgen;
98
+static bool add_cpufreq_dev __initdata;
10099 
101100 static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
102101 {
....@@ -245,6 +244,66 @@
245244 	},
246245 };
247246 
247
+static const struct clockgen_muxinfo ls1021a_cmux = {
248
+	{
249
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
250
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
251
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
252
+	}
253
+};
254
+
255
+static const struct clockgen_muxinfo ls1028a_hwa1 = {
256
+	{
257
+		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
258
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
259
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
260
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
261
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
262
+		{},
263
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
264
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
265
+	},
266
+};
267
+
268
+static const struct clockgen_muxinfo ls1028a_hwa2 = {
269
+	{
270
+		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
271
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
272
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
273
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
274
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
275
+		{},
276
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
277
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
278
+	},
279
+};
280
+
281
+static const struct clockgen_muxinfo ls1028a_hwa3 = {
282
+	{
283
+		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
284
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
285
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
286
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
287
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
288
+		{},
289
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
290
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
291
+	},
292
+};
293
+
294
+static const struct clockgen_muxinfo ls1028a_hwa4 = {
295
+	{
296
+		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
297
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
298
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
299
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
300
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
301
+		{},
302
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
303
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
304
+	},
305
+};
306
+
248307 static const struct clockgen_muxinfo ls1043a_hwa1 = {
249308 	{
250309 		{},
....@@ -289,6 +348,32 @@
289348 		{},
290349 		{},
291350 		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
351
+	},
352
+};
353
+
354
+static const struct clockgen_muxinfo ls1088a_hwa1 = {
355
+	{
356
+		{},
357
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
358
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
359
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
360
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
361
+		{},
362
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
363
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
364
+	},
365
+};
366
+
367
+static const struct clockgen_muxinfo ls1088a_hwa2 = {
368
+	{
369
+		{},
370
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
371
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
372
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
373
+		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
374
+		{},
375
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
376
+		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
292377 	},
293378 };
294379 
....@@ -500,12 +585,27 @@
500585 	{
501586 		.compat = "fsl,ls1021a-clockgen",
502587 		.cmux_groups = {
503
-			&t1023_cmux
588
+			&ls1021a_cmux
504589 		},
505590 		.cmux_to_group = {
506591 			0, -1
507592 		},
508593 		.pll_mask = 0x03,
594
+	},
595
+	{
596
+		.compat = "fsl,ls1028a-clockgen",
597
+		.cmux_groups = {
598
+			&clockgen2_cmux_cga12
599
+		},
600
+		.hwaccel = {
601
+			&ls1028a_hwa1, &ls1028a_hwa2,
602
+			&ls1028a_hwa3, &ls1028a_hwa4
603
+		},
604
+		.cmux_to_group = {
605
+			0, 0, 0, 0, -1
606
+		},
607
+		.pll_mask = 0x07,
608
+		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
509609 	},
510610 	{
511611 		.compat = "fsl,ls1043a-clockgen",
....@@ -542,6 +642,9 @@
542642 		.cmux_groups = {
543643 			&clockgen2_cmux_cga12
544644 		},
645
+		.hwaccel = {
646
+			&ls1088a_hwa1, &ls1088a_hwa2
647
+		},
545648 		.cmux_to_group = {
546649 			0, 0, -1
547650 		},
....@@ -565,6 +668,17 @@
565668 		},
566669 		.cmux_to_group = {
567670 			0, 0, 1, 1, -1
671
+		},
672
+		.pll_mask = 0x37,
673
+		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
674
+	},
675
+	{
676
+		.compat = "fsl,lx2160a-clockgen",
677
+		.cmux_groups = {
678
+			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
679
+		},
680
+		.cmux_to_group = {
681
+			0, 0, 0, 0, 1, 1, 1, 1, -1
568682 		},
569683 		.pll_mask = 0x37,
570684 		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
....@@ -601,7 +715,7 @@
601715 			&p4080_cmux_grp1, &p4080_cmux_grp2
602716 		},
603717 		.cmux_to_group = {
604
-			0, 0, 0, 0, 1, 1, 1, 1
718
+			0, 0, 0, 0, 1, 1, 1, 1, -1
605719 		},
606720 		.pll_mask = 0x1f,
607721 	},
....@@ -914,7 +1028,7 @@
9141028 	}
9151029 }
9161030 
917
-static void __init clockgen_init(struct device_node *np);
1031
+static void __init _clockgen_init(struct device_node *np, bool legacy);
9181032 
9191033 /*
9201034  * Legacy nodes may get probed before the parent clockgen node.
....@@ -924,8 +1038,13 @@
9241038  */
9251039 static void __init legacy_init_clockgen(struct device_node *np)
9261040 {
927
-	if (!clockgen.node)
928
-		clockgen_init(of_get_parent(np));
1041
+	if (!clockgen.node) {
1042
+		struct device_node *parent_np;
1043
+
1044
+		parent_np = of_get_parent(np);
1045
+		_clockgen_init(parent_np, true);
1046
+		of_node_put(parent_np);
1047
+	}
9291048 }
9301049 
9311050 /* Legacy node */
....@@ -945,8 +1064,8 @@
9451064 
9461065 	rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
9471066 	if (rc) {
948
-		pr_err("%s: Couldn't register clk provider for node %s: %d\n",
949
-		       __func__, np->name, rc);
1067
+		pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1068
+		       __func__, np, rc);
9501069 		return;
9511070 	}
9521071 }
....@@ -1020,6 +1139,7 @@
10201139 	sysclk = of_get_child_by_name(clockgen.node, "sysclk");
10211140 	if (sysclk) {
10221141 		clk = sysclk_from_fixed(sysclk, name);
1142
+		of_node_put(sysclk);
10231143 		if (!IS_ERR(clk))
10241144 			return clk;
10251145 	}
....@@ -1128,7 +1248,7 @@
11281248 		int ret;
11291249 
11301250 		/*
1131
-		 * For platform PLL, there are 8 divider clocks.
1251
+		 * For platform PLL, there are MAX_PLL_DIV divider clocks.
11321252 		 * For core PLL, there are 4 divider clocks at most.
11331253 		 */
11341254 		if (idx != PLATFORM_PLL && i >= 4)
....@@ -1148,8 +1268,8 @@
11481268 		pll->div[i].clk = clk;
11491269 		ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
11501270 		if (ret != 0)
1151
-			pr_err("%s: %s: register to lookup table failed %ld\n",
1152
-			       __func__, pll->div[i].name, PTR_ERR(clk));
1271
+			pr_err("%s: %s: register to lookup table failed %d\n",
1272
+			       __func__, pll->div[i].name, ret);
11531273 
11541274 	}
11551275 }
....@@ -1199,8 +1319,8 @@
11991319 
12001320 	rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
12011321 	if (rc) {
1202
-		pr_err("%s: Couldn't register clk provider for node %s: %d\n",
1203
-		       __func__, np->name, rc);
1322
+		pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1323
+		       __func__, np, rc);
12041324 		goto err_cell;
12051325 	}
12061326 
....@@ -1342,7 +1462,7 @@
13421462 }
13431463 #endif
13441464 
1345
-static void __init clockgen_init(struct device_node *np)
1465
+static void __init _clockgen_init(struct device_node *np, bool legacy)
13461466 {
13471467 	int i, ret;
13481468 	bool is_old_ls1021a = false;
....@@ -1360,7 +1480,7 @@
13601480 		is_old_ls1021a = true;
13611481 	}
13621482 	if (!clockgen.regs) {
1363
-		pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name);
1483
+		pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
13641484 		return;
13651485 	}
13661486 
....@@ -1407,9 +1527,12 @@
14071527 
14081528 	ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
14091529 	if (ret) {
1410
-		pr_err("%s: Couldn't register clk provider for node %s: %d\n",
1411
-		       __func__, np->name, ret);
1530
+		pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1531
+		       __func__, np, ret);
14121532 	}
1533
+
1534
+	/* Don't create cpufreq device for legacy clockgen blocks */
1535
+	add_cpufreq_dev = !legacy;
14131536 
14141537 	return;
14151538 err:
....@@ -1417,14 +1540,47 @@
14171540 	clockgen.regs = NULL;
14181541 }
14191542 
1543
+static void __init clockgen_init(struct device_node *np)
1544
+{
1545
+	_clockgen_init(np, false);
1546
+}
1547
+
1548
+static int __init clockgen_cpufreq_init(void)
1549
+{
1550
+	struct platform_device *pdev;
1551
+
1552
+	if (add_cpufreq_dev) {
1553
+		pdev = platform_device_register_simple("qoriq-cpufreq", -1,
1554
+				NULL, 0);
1555
+		if (IS_ERR(pdev))
1556
+			pr_err("Couldn't register qoriq-cpufreq err=%ld\n",
1557
+				PTR_ERR(pdev));
1558
+	}
1559
+	return 0;
1560
+}
1561
+device_initcall(clockgen_cpufreq_init);
1562
+
14201563 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
14211564 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1565
+CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
1566
+CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
14221567 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
14231568 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1569
+CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
14241570 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
14251571 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
14261572 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
14271573 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1574
+CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
1575
+CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
1576
+CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
1577
+CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
1578
+CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
1579
+CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
1580
+CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
1581
+CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
1582
+CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
1583
+CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
14281584 
14291585 /* Legacy nodes */
14301586 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);