.. | .. |
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732 | 732 | int i, ret; |
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733 | 733 | struct iproc_pll *pll; |
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734 | 734 | struct iproc_clk *iclk; |
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735 | | - struct clk_init_data init = {}; |
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| 735 | + struct clk_init_data init; |
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736 | 736 | const char *parent_name; |
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737 | 737 | struct iproc_clk *iclk_array; |
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738 | 738 | struct clk_hw_onecell_data *clk_data; |
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| 739 | + const char *clk_name; |
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739 | 740 | |
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740 | 741 | if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) |
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741 | 742 | return; |
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.. | .. |
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783 | 784 | iclk = &iclk_array[0]; |
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784 | 785 | iclk->pll = pll; |
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785 | 786 | |
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786 | | - init.name = node->name; |
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| 787 | + ret = of_property_read_string_index(node, "clock-output-names", |
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| 788 | + 0, &clk_name); |
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| 789 | + if (WARN_ON(ret)) |
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| 790 | + goto err_pll_register; |
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| 791 | + |
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| 792 | + init.name = clk_name; |
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787 | 793 | init.ops = &iproc_pll_ops; |
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788 | 794 | init.flags = 0; |
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789 | 795 | parent_name = of_clk_get_parent_name(node, 0); |
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.. | .. |
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803 | 809 | goto err_pll_register; |
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804 | 810 | |
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805 | 811 | clk_data->hws[0] = &iclk->hw; |
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| 812 | + parent_name = clk_name; |
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806 | 813 | |
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807 | 814 | /* now initialize and register all leaf clocks */ |
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808 | 815 | for (i = 1; i < num_clks; i++) { |
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809 | | - const char *clk_name; |
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810 | | - |
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811 | 816 | memset(&init, 0, sizeof(init)); |
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812 | | - parent_name = node->name; |
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813 | 817 | |
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814 | 818 | ret = of_property_read_string_index(node, "clock-output-names", |
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815 | 819 | i, &clk_name); |
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