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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/drivers/clk/bcm/clk-bcm2835.c
....@@ -1,17 +1,7 @@
1
+// SPDX-License-Identifier: GPL-2.0+
12 /*
23  * Copyright (C) 2010,2015 Broadcom
34  * Copyright (C) 2012 Stephen Warren
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
14
- *
155  */
166 
177 /**
....@@ -39,8 +29,9 @@
3929 #include <linux/clk.h>
4030 #include <linux/debugfs.h>
4131 #include <linux/delay.h>
32
+#include <linux/io.h>
4233 #include <linux/module.h>
43
-#include <linux/of.h>
34
+#include <linux/of_device.h>
4435 #include <linux/platform_device.h>
4536 #include <linux/slab.h>
4637 #include <dt-bindings/clock/bcm2835.h>
....@@ -123,6 +114,8 @@
123114 #define CM_AVEODIV		0x1bc
124115 #define CM_EMMCCTL		0x1c0
125116 #define CM_EMMCDIV		0x1c4
117
+#define CM_EMMC2CTL		0x1d0
118
+#define CM_EMMC2DIV		0x1d4
126119 
127120 /* General bits for the CM_*CTL regs */
128121 # define CM_ENABLE			BIT(4)
....@@ -298,6 +291,10 @@
298291 #define LOCK_TIMEOUT_NS		100000000
299292 #define BCM2835_MAX_FB_RATE	1750000000u
300293 
294
+#define SOC_BCM2835		BIT(0)
295
+#define SOC_BCM2711		BIT(1)
296
+#define SOC_ALL			(SOC_BCM2835 | SOC_BCM2711)
297
+
301298 /*
302299  * Names of clocks used within the driver that need to be replaced
303300  * with an external parent's name.  This array is in the order that
....@@ -317,6 +314,7 @@
317314 	struct device *dev;
318315 	void __iomem *regs;
319316 	spinlock_t regs_lock; /* spinlock for all clocks */
317
+	unsigned int soc;
320318 
321319 	/*
322320 	 * Real names of cprman clock parents looked up through
....@@ -327,6 +325,10 @@
327325 
328326 	/* Must be last */
329327 	struct clk_hw_onecell_data onecell;
328
+};
329
+
330
+struct cprman_plat_data {
331
+	unsigned int soc;
330332 };
331333 
332334 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
....@@ -395,8 +397,8 @@
395397 }
396398 
397399 static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
398
-				  struct debugfs_reg32 *regs, size_t nregs,
399
-				  struct dentry *dentry)
400
+				   const struct debugfs_reg32 *regs,
401
+				   size_t nregs, struct dentry *dentry)
400402 {
401403 	struct debugfs_regset32 *regset;
402404 
....@@ -420,6 +422,7 @@
420422 	u32 reference_enable_mask;
421423 	/* Bit in CM_LOCK to indicate when the PLL has locked. */
422424 	u32 lock_mask;
425
+	u32 flags;
423426 
424427 	const struct bcm2835_pll_ana_bits *ana;
425428 
....@@ -524,6 +527,20 @@
524527 		A2W_PLL_CTRL_PRST_DISABLE;
525528 }
526529 
530
+static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman,
531
+				       const struct bcm2835_pll_data *data)
532
+{
533
+	/*
534
+	 * On BCM2711 there isn't a pre-divisor available in the PLL feedback
535
+	 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed
536
+	 * for to for VCO RANGE bits.
537
+	 */
538
+	if (cprman->soc & SOC_BCM2711)
539
+		return 0;
540
+
541
+	return data->ana->fb_prediv_mask;
542
+}
543
+
527544 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
528545 					     unsigned long parent_rate,
529546 					     u32 *ndiv, u32 *fdiv)
....@@ -581,7 +598,7 @@
581598 	ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
582599 	pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
583600 	using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
584
-		data->ana->fb_prediv_mask;
601
+		       bcm2835_pll_get_prediv_mask(cprman, data);
585602 
586603 	if (using_prediv) {
587604 		ndiv *= 2;
....@@ -664,6 +681,7 @@
664681 	struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
665682 	struct bcm2835_cprman *cprman = pll->cprman;
666683 	const struct bcm2835_pll_data *data = pll->data;
684
+	u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data);
667685 	bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
668686 	u32 ndiv, fdiv, a2w_ctl;
669687 	u32 ana[4];
....@@ -681,7 +699,7 @@
681699 	for (i = 3; i >= 0; i--)
682700 		ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
683701 
684
-	was_using_prediv = ana[1] & data->ana->fb_prediv_mask;
702
+	was_using_prediv = ana[1] & prediv_mask;
685703 
686704 	ana[0] &= ~data->ana->mask0;
687705 	ana[0] |= data->ana->set0;
....@@ -691,10 +709,10 @@
691709 	ana[3] |= data->ana->set3;
692710 
693711 	if (was_using_prediv && !use_fb_prediv) {
694
-		ana[1] &= ~data->ana->fb_prediv_mask;
712
+		ana[1] &= ~prediv_mask;
695713 		do_ana_setup_first = true;
696714 	} else if (!was_using_prediv && use_fb_prediv) {
697
-		ana[1] |= data->ana->fb_prediv_mask;
715
+		ana[1] |= prediv_mask;
698716 		do_ana_setup_first = false;
699717 	} else {
700718 		do_ana_setup_first = true;
....@@ -950,9 +968,9 @@
950968 	return div;
951969 }
952970 
953
-static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
954
-					    unsigned long parent_rate,
955
-					    u32 div)
971
+static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
972
+						     unsigned long parent_rate,
973
+						     u32 div)
956974 {
957975 	const struct bcm2835_clock_data *data = clock->data;
958976 	u64 temp;
....@@ -1234,7 +1252,7 @@
12341252 	return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
12351253 }
12361254 
1237
-static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
1255
+static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
12381256 	{
12391257 		.name = "ctl",
12401258 		.offset = 0,
....@@ -1290,10 +1308,11 @@
12901308 };
12911309 
12921310 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
1293
-					   const struct bcm2835_pll_data *data)
1311
+					   const void *data)
12941312 {
1313
+	const struct bcm2835_pll_data *pll_data = data;
12951314 	struct bcm2835_pll *pll;
1296
-	struct clk_init_data init = {};
1315
+	struct clk_init_data init;
12971316 	int ret;
12981317 
12991318 	memset(&init, 0, sizeof(init));
....@@ -1301,16 +1320,16 @@
13011320 	/* All of the PLLs derive from the external oscillator. */
13021321 	init.parent_names = &cprman->real_parent_names[0];
13031322 	init.num_parents = 1;
1304
-	init.name = data->name;
1323
+	init.name = pll_data->name;
13051324 	init.ops = &bcm2835_pll_clk_ops;
1306
-	init.flags = CLK_IGNORE_UNUSED;
1325
+	init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
13071326 
13081327 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
13091328 	if (!pll)
13101329 		return NULL;
13111330 
13121331 	pll->cprman = cprman;
1313
-	pll->data = data;
1332
+	pll->data = pll_data;
13141333 	pll->hw.init = &init;
13151334 
13161335 	ret = devm_clk_hw_register(cprman->dev, &pll->hw);
....@@ -1323,35 +1342,36 @@
13231342 
13241343 static struct clk_hw *
13251344 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
1326
-			     const struct bcm2835_pll_divider_data *data)
1345
+			     const void *data)
13271346 {
1347
+	const struct bcm2835_pll_divider_data *divider_data = data;
13281348 	struct bcm2835_pll_divider *divider;
1329
-	struct clk_init_data init = {};
1349
+	struct clk_init_data init;
13301350 	const char *divider_name;
13311351 	int ret;
13321352 
1333
-	if (data->fixed_divider != 1) {
1353
+	if (divider_data->fixed_divider != 1) {
13341354 		divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1335
-					      "%s_prediv", data->name);
1355
+					      "%s_prediv", divider_data->name);
13361356 		if (!divider_name)
13371357 			return NULL;
13381358 	} else {
1339
-		divider_name = data->name;
1359
+		divider_name = divider_data->name;
13401360 	}
13411361 
13421362 	memset(&init, 0, sizeof(init));
13431363 
1344
-	init.parent_names = &data->source_pll;
1364
+	init.parent_names = &divider_data->source_pll;
13451365 	init.num_parents = 1;
13461366 	init.name = divider_name;
13471367 	init.ops = &bcm2835_pll_divider_clk_ops;
1348
-	init.flags = data->flags | CLK_IGNORE_UNUSED;
1368
+	init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
13491369 
13501370 	divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
13511371 	if (!divider)
13521372 		return NULL;
13531373 
1354
-	divider->div.reg = cprman->regs + data->a2w_reg;
1374
+	divider->div.reg = cprman->regs + divider_data->a2w_reg;
13551375 	divider->div.shift = A2W_PLL_DIV_SHIFT;
13561376 	divider->div.width = A2W_PLL_DIV_BITS;
13571377 	divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
....@@ -1360,7 +1380,7 @@
13601380 	divider->div.table = NULL;
13611381 
13621382 	divider->cprman = cprman;
1363
-	divider->data = data;
1383
+	divider->data = divider_data;
13641384 
13651385 	ret = devm_clk_hw_register(cprman->dev, &divider->div.hw);
13661386 	if (ret)
....@@ -1370,22 +1390,24 @@
13701390 	 * PLLH's channels have a fixed divide by 10 afterwards, which
13711391 	 * is what our consumers are actually using.
13721392 	 */
1373
-	if (data->fixed_divider != 1) {
1374
-		return clk_hw_register_fixed_factor(cprman->dev, data->name,
1393
+	if (divider_data->fixed_divider != 1) {
1394
+		return clk_hw_register_fixed_factor(cprman->dev,
1395
+						    divider_data->name,
13751396 						    divider_name,
13761397 						    CLK_SET_RATE_PARENT,
13771398 						    1,
1378
-						    data->fixed_divider);
1399
+						    divider_data->fixed_divider);
13791400 	}
13801401 
13811402 	return &divider->div.hw;
13821403 }
13831404 
13841405 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
1385
-					  const struct bcm2835_clock_data *data)
1406
+					     const void *data)
13861407 {
1408
+	const struct bcm2835_clock_data *clock_data = data;
13871409 	struct bcm2835_clock *clock;
1388
-	struct clk_init_data init = {};
1410
+	struct clk_init_data init;
13891411 	const char *parents[1 << CM_SRC_BITS];
13901412 	size_t i;
13911413 	int ret;
....@@ -1394,8 +1416,8 @@
13941416 	 * Replace our strings referencing parent clocks with the
13951417 	 * actual clock-output-name of the parent.
13961418 	 */
1397
-	for (i = 0; i < data->num_mux_parents; i++) {
1398
-		parents[i] = data->parents[i];
1419
+	for (i = 0; i < clock_data->num_mux_parents; i++) {
1420
+		parents[i] = clock_data->parents[i];
13991421 
14001422 		ret = match_string(cprman_parent_names,
14011423 				   ARRAY_SIZE(cprman_parent_names),
....@@ -1406,18 +1428,18 @@
14061428 
14071429 	memset(&init, 0, sizeof(init));
14081430 	init.parent_names = parents;
1409
-	init.num_parents = data->num_mux_parents;
1410
-	init.name = data->name;
1411
-	init.flags = data->flags | CLK_IGNORE_UNUSED;
1431
+	init.num_parents = clock_data->num_mux_parents;
1432
+	init.name = clock_data->name;
1433
+	init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
14121434 
14131435 	/*
14141436 	 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
14151437 	 * rate changes on at least of the parents.
14161438 	 */
1417
-	if (data->set_rate_parent)
1439
+	if (clock_data->set_rate_parent)
14181440 		init.flags |= CLK_SET_RATE_PARENT;
14191441 
1420
-	if (data->is_vpu_clock) {
1442
+	if (clock_data->is_vpu_clock) {
14211443 		init.ops = &bcm2835_vpu_clock_clk_ops;
14221444 	} else {
14231445 		init.ops = &bcm2835_clock_clk_ops;
....@@ -1426,7 +1448,7 @@
14261448 		/* If the clock wasn't actually enabled at boot, it's not
14271449 		 * critical.
14281450 		 */
1429
-		if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE))
1451
+		if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
14301452 			init.flags &= ~CLK_IS_CRITICAL;
14311453 	}
14321454 
....@@ -1435,7 +1457,7 @@
14351457 		return NULL;
14361458 
14371459 	clock->cprman = cprman;
1438
-	clock->data = data;
1460
+	clock->data = clock_data;
14391461 	clock->hw.init = &init;
14401462 
14411463 	ret = devm_clk_hw_register(cprman->dev, &clock->hw);
....@@ -1445,34 +1467,42 @@
14451467 }
14461468 
14471469 static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
1448
-					 const struct bcm2835_gate_data *data)
1470
+					    const void *data)
14491471 {
1450
-	return clk_hw_register_gate(cprman->dev, data->name, data->parent,
1472
+	const struct bcm2835_gate_data *gate_data = data;
1473
+
1474
+	return clk_hw_register_gate(cprman->dev, gate_data->name,
1475
+				    gate_data->parent,
14511476 				    CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
1452
-				    cprman->regs + data->ctl_reg,
1477
+				    cprman->regs + gate_data->ctl_reg,
14531478 				    CM_GATE_BIT, 0, &cprman->regs_lock);
14541479 }
14551480 
1456
-typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
1457
-					       const void *data);
14581481 struct bcm2835_clk_desc {
1459
-	bcm2835_clk_register clk_register;
1482
+	struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,
1483
+				       const void *data);
1484
+	unsigned int supported;
14601485 	const void *data;
14611486 };
14621487 
14631488 /* assignment helper macros for different clock types */
1464
-#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
1465
-			    .data = __VA_ARGS__ }
1466
-#define REGISTER_PLL(...)	_REGISTER(&bcm2835_register_pll,	\
1489
+#define _REGISTER(f, s, ...) { .clk_register = f, \
1490
+			       .supported = s,				\
1491
+			       .data = __VA_ARGS__ }
1492
+#define REGISTER_PLL(s, ...)	_REGISTER(&bcm2835_register_pll,	\
1493
+					  s,				\
14671494 					  &(struct bcm2835_pll_data)	\
14681495 					  {__VA_ARGS__})
1469
-#define REGISTER_PLL_DIV(...)	_REGISTER(&bcm2835_register_pll_divider, \
1470
-					  &(struct bcm2835_pll_divider_data) \
1471
-					  {__VA_ARGS__})
1472
-#define REGISTER_CLK(...)	_REGISTER(&bcm2835_register_clock,	\
1496
+#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
1497
+					   s,				  \
1498
+					   &(struct bcm2835_pll_divider_data) \
1499
+					   {__VA_ARGS__})
1500
+#define REGISTER_CLK(s, ...)	_REGISTER(&bcm2835_register_clock,	\
1501
+					  s,				\
14731502 					  &(struct bcm2835_clock_data)	\
14741503 					  {__VA_ARGS__})
1475
-#define REGISTER_GATE(...)	_REGISTER(&bcm2835_register_gate,	\
1504
+#define REGISTER_GATE(s, ...)	_REGISTER(&bcm2835_register_gate,	\
1505
+					  s,				\
14761506 					  &(struct bcm2835_gate_data)	\
14771507 					  {__VA_ARGS__})
14781508 
....@@ -1486,7 +1516,8 @@
14861516 	"testdebug1"
14871517 };
14881518 
1489
-#define REGISTER_OSC_CLK(...)	REGISTER_CLK(				\
1519
+#define REGISTER_OSC_CLK(s, ...)	REGISTER_CLK(			\
1520
+	s,								\
14901521 	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),	\
14911522 	.parents = bcm2835_clock_osc_parents,				\
14921523 	__VA_ARGS__)
....@@ -1503,7 +1534,8 @@
15031534 	"pllh_aux",
15041535 };
15051536 
1506
-#define REGISTER_PER_CLK(...)	REGISTER_CLK(				\
1537
+#define REGISTER_PER_CLK(s, ...)	REGISTER_CLK(			\
1538
+	s,								\
15071539 	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),	\
15081540 	.parents = bcm2835_clock_per_parents,				\
15091541 	__VA_ARGS__)
....@@ -1528,7 +1560,8 @@
15281560 	"-",
15291561 };
15301562 
1531
-#define REGISTER_PCM_CLK(...)	REGISTER_CLK(				\
1563
+#define REGISTER_PCM_CLK(s, ...)	REGISTER_CLK(			\
1564
+	s,								\
15321565 	.num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents),		\
15331566 	.parents = bcm2835_pcm_per_parents,				\
15341567 	__VA_ARGS__)
....@@ -1547,7 +1580,8 @@
15471580 	"pllc_core2",
15481581 };
15491582 
1550
-#define REGISTER_VPU_CLK(...)	REGISTER_CLK(				\
1583
+#define REGISTER_VPU_CLK(s, ...)	REGISTER_CLK(			\
1584
+	s,								\
15511585 	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),	\
15521586 	.parents = bcm2835_clock_vpu_parents,				\
15531587 	__VA_ARGS__)
....@@ -1583,12 +1617,14 @@
15831617 	"dsi1_byte_inv",
15841618 };
15851619 
1586
-#define REGISTER_DSI0_CLK(...)	REGISTER_CLK(				\
1620
+#define REGISTER_DSI0_CLK(s, ...)	REGISTER_CLK(			\
1621
+	s,								\
15871622 	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents),	\
15881623 	.parents = bcm2835_clock_dsi0_parents,				\
15891624 	__VA_ARGS__)
15901625 
1591
-#define REGISTER_DSI1_CLK(...)	REGISTER_CLK(				\
1626
+#define REGISTER_DSI1_CLK(s, ...)	REGISTER_CLK(			\
1627
+	s,								\
15921628 	.num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents),	\
15931629 	.parents = bcm2835_clock_dsi1_parents,				\
15941630 	__VA_ARGS__)
....@@ -1608,6 +1644,7 @@
16081644 	 * AUDIO domain is on.
16091645 	 */
16101646 	[BCM2835_PLLA]		= REGISTER_PLL(
1647
+		SOC_ALL,
16111648 		.name = "plla",
16121649 		.cm_ctrl_reg = CM_PLLA,
16131650 		.a2w_ctrl_reg = A2W_PLLA_CTRL,
....@@ -1622,6 +1659,7 @@
16221659 		.max_rate = 2400000000u,
16231660 		.max_fb_rate = BCM2835_MAX_FB_RATE),
16241661 	[BCM2835_PLLA_CORE]	= REGISTER_PLL_DIV(
1662
+		SOC_ALL,
16251663 		.name = "plla_core",
16261664 		.source_pll = "plla",
16271665 		.cm_reg = CM_PLLA,
....@@ -1631,6 +1669,7 @@
16311669 		.fixed_divider = 1,
16321670 		.flags = CLK_SET_RATE_PARENT),
16331671 	[BCM2835_PLLA_PER]	= REGISTER_PLL_DIV(
1672
+		SOC_ALL,
16341673 		.name = "plla_per",
16351674 		.source_pll = "plla",
16361675 		.cm_reg = CM_PLLA,
....@@ -1640,6 +1679,7 @@
16401679 		.fixed_divider = 1,
16411680 		.flags = CLK_SET_RATE_PARENT),
16421681 	[BCM2835_PLLA_DSI0]	= REGISTER_PLL_DIV(
1682
+		SOC_ALL,
16431683 		.name = "plla_dsi0",
16441684 		.source_pll = "plla",
16451685 		.cm_reg = CM_PLLA,
....@@ -1648,6 +1688,7 @@
16481688 		.hold_mask = CM_PLLA_HOLDDSI0,
16491689 		.fixed_divider = 1),
16501690 	[BCM2835_PLLA_CCP2]	= REGISTER_PLL_DIV(
1691
+		SOC_ALL,
16511692 		.name = "plla_ccp2",
16521693 		.source_pll = "plla",
16531694 		.cm_reg = CM_PLLA,
....@@ -1659,6 +1700,7 @@
16591700 
16601701 	/* PLLB is used for the ARM's clock. */
16611702 	[BCM2835_PLLB]		= REGISTER_PLL(
1703
+		SOC_ALL,
16621704 		.name = "pllb",
16631705 		.cm_ctrl_reg = CM_PLLB,
16641706 		.a2w_ctrl_reg = A2W_PLLB_CTRL,
....@@ -1671,8 +1713,10 @@
16711713 
16721714 		.min_rate = 600000000u,
16731715 		.max_rate = 3000000000u,
1674
-		.max_fb_rate = BCM2835_MAX_FB_RATE),
1716
+		.max_fb_rate = BCM2835_MAX_FB_RATE,
1717
+		.flags = CLK_GET_RATE_NOCACHE),
16751718 	[BCM2835_PLLB_ARM]	= REGISTER_PLL_DIV(
1719
+		SOC_ALL,
16761720 		.name = "pllb_arm",
16771721 		.source_pll = "pllb",
16781722 		.cm_reg = CM_PLLB,
....@@ -1680,7 +1724,7 @@
16801724 		.load_mask = CM_PLLB_LOADARM,
16811725 		.hold_mask = CM_PLLB_HOLDARM,
16821726 		.fixed_divider = 1,
1683
-		.flags = CLK_SET_RATE_PARENT),
1727
+		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
16841728 
16851729 	/*
16861730 	 * PLLC is the core PLL, used to drive the core VPU clock.
....@@ -1689,6 +1733,7 @@
16891733 	 * AUDIO domain is on.
16901734 	 */
16911735 	[BCM2835_PLLC]		= REGISTER_PLL(
1736
+		SOC_ALL,
16921737 		.name = "pllc",
16931738 		.cm_ctrl_reg = CM_PLLC,
16941739 		.a2w_ctrl_reg = A2W_PLLC_CTRL,
....@@ -1703,6 +1748,7 @@
17031748 		.max_rate = 3000000000u,
17041749 		.max_fb_rate = BCM2835_MAX_FB_RATE),
17051750 	[BCM2835_PLLC_CORE0]	= REGISTER_PLL_DIV(
1751
+		SOC_ALL,
17061752 		.name = "pllc_core0",
17071753 		.source_pll = "pllc",
17081754 		.cm_reg = CM_PLLC,
....@@ -1712,6 +1758,7 @@
17121758 		.fixed_divider = 1,
17131759 		.flags = CLK_SET_RATE_PARENT),
17141760 	[BCM2835_PLLC_CORE1]	= REGISTER_PLL_DIV(
1761
+		SOC_ALL,
17151762 		.name = "pllc_core1",
17161763 		.source_pll = "pllc",
17171764 		.cm_reg = CM_PLLC,
....@@ -1721,6 +1768,7 @@
17211768 		.fixed_divider = 1,
17221769 		.flags = CLK_SET_RATE_PARENT),
17231770 	[BCM2835_PLLC_CORE2]	= REGISTER_PLL_DIV(
1771
+		SOC_ALL,
17241772 		.name = "pllc_core2",
17251773 		.source_pll = "pllc",
17261774 		.cm_reg = CM_PLLC,
....@@ -1730,6 +1778,7 @@
17301778 		.fixed_divider = 1,
17311779 		.flags = CLK_SET_RATE_PARENT),
17321780 	[BCM2835_PLLC_PER]	= REGISTER_PLL_DIV(
1781
+		SOC_ALL,
17331782 		.name = "pllc_per",
17341783 		.source_pll = "pllc",
17351784 		.cm_reg = CM_PLLC,
....@@ -1737,7 +1786,7 @@
17371786 		.load_mask = CM_PLLC_LOADPER,
17381787 		.hold_mask = CM_PLLC_HOLDPER,
17391788 		.fixed_divider = 1,
1740
-		.flags = CLK_SET_RATE_PARENT),
1789
+		.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
17411790 
17421791 	/*
17431792 	 * PLLD is the display PLL, used to drive DSI display panels.
....@@ -1746,6 +1795,7 @@
17461795 	 * AUDIO domain is on.
17471796 	 */
17481797 	[BCM2835_PLLD]		= REGISTER_PLL(
1798
+		SOC_ALL,
17491799 		.name = "plld",
17501800 		.cm_ctrl_reg = CM_PLLD,
17511801 		.a2w_ctrl_reg = A2W_PLLD_CTRL,
....@@ -1760,6 +1810,7 @@
17601810 		.max_rate = 2400000000u,
17611811 		.max_fb_rate = BCM2835_MAX_FB_RATE),
17621812 	[BCM2835_PLLD_CORE]	= REGISTER_PLL_DIV(
1813
+		SOC_ALL,
17631814 		.name = "plld_core",
17641815 		.source_pll = "plld",
17651816 		.cm_reg = CM_PLLD,
....@@ -1768,7 +1819,13 @@
17681819 		.hold_mask = CM_PLLD_HOLDCORE,
17691820 		.fixed_divider = 1,
17701821 		.flags = CLK_SET_RATE_PARENT),
1822
+	/*
1823
+	 * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core.
1824
+	 * Otherwise this could cause firmware lookups. That's why we mark
1825
+	 * it as critical.
1826
+	 */
17711827 	[BCM2835_PLLD_PER]	= REGISTER_PLL_DIV(
1828
+		SOC_ALL,
17721829 		.name = "plld_per",
17731830 		.source_pll = "plld",
17741831 		.cm_reg = CM_PLLD,
....@@ -1776,8 +1833,9 @@
17761833 		.load_mask = CM_PLLD_LOADPER,
17771834 		.hold_mask = CM_PLLD_HOLDPER,
17781835 		.fixed_divider = 1,
1779
-		.flags = CLK_SET_RATE_PARENT),
1836
+		.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
17801837 	[BCM2835_PLLD_DSI0]	= REGISTER_PLL_DIV(
1838
+		SOC_ALL,
17811839 		.name = "plld_dsi0",
17821840 		.source_pll = "plld",
17831841 		.cm_reg = CM_PLLD,
....@@ -1786,6 +1844,7 @@
17861844 		.hold_mask = CM_PLLD_HOLDDSI0,
17871845 		.fixed_divider = 1),
17881846 	[BCM2835_PLLD_DSI1]	= REGISTER_PLL_DIV(
1847
+		SOC_ALL,
17891848 		.name = "plld_dsi1",
17901849 		.source_pll = "plld",
17911850 		.cm_reg = CM_PLLD,
....@@ -1801,6 +1860,7 @@
18011860 	 * It is in the HDMI power domain.
18021861 	 */
18031862 	[BCM2835_PLLH]		= REGISTER_PLL(
1863
+		SOC_BCM2835,
18041864 		"pllh",
18051865 		.cm_ctrl_reg = CM_PLLH,
18061866 		.a2w_ctrl_reg = A2W_PLLH_CTRL,
....@@ -1815,6 +1875,7 @@
18151875 		.max_rate = 3000000000u,
18161876 		.max_fb_rate = BCM2835_MAX_FB_RATE),
18171877 	[BCM2835_PLLH_RCAL]	= REGISTER_PLL_DIV(
1878
+		SOC_BCM2835,
18181879 		.name = "pllh_rcal",
18191880 		.source_pll = "pllh",
18201881 		.cm_reg = CM_PLLH,
....@@ -1824,6 +1885,7 @@
18241885 		.fixed_divider = 10,
18251886 		.flags = CLK_SET_RATE_PARENT),
18261887 	[BCM2835_PLLH_AUX]	= REGISTER_PLL_DIV(
1888
+		SOC_BCM2835,
18271889 		.name = "pllh_aux",
18281890 		.source_pll = "pllh",
18291891 		.cm_reg = CM_PLLH,
....@@ -1833,6 +1895,7 @@
18331895 		.fixed_divider = 1,
18341896 		.flags = CLK_SET_RATE_PARENT),
18351897 	[BCM2835_PLLH_PIX]	= REGISTER_PLL_DIV(
1898
+		SOC_BCM2835,
18361899 		.name = "pllh_pix",
18371900 		.source_pll = "pllh",
18381901 		.cm_reg = CM_PLLH,
....@@ -1848,6 +1911,7 @@
18481911 
18491912 	/* One Time Programmable Memory clock.  Maximum 10Mhz. */
18501913 	[BCM2835_CLOCK_OTP]	= REGISTER_OSC_CLK(
1914
+		SOC_ALL,
18511915 		.name = "otp",
18521916 		.ctl_reg = CM_OTPCTL,
18531917 		.div_reg = CM_OTPDIV,
....@@ -1859,6 +1923,7 @@
18591923 	 * bythe watchdog timer and the camera pulse generator.
18601924 	 */
18611925 	[BCM2835_CLOCK_TIMER]	= REGISTER_OSC_CLK(
1926
+		SOC_ALL,
18621927 		.name = "timer",
18631928 		.ctl_reg = CM_TIMERCTL,
18641929 		.div_reg = CM_TIMERDIV,
....@@ -1869,12 +1934,14 @@
18691934 	 * Generally run at 2Mhz, max 5Mhz.
18701935 	 */
18711936 	[BCM2835_CLOCK_TSENS]	= REGISTER_OSC_CLK(
1937
+		SOC_ALL,
18721938 		.name = "tsens",
18731939 		.ctl_reg = CM_TSENSCTL,
18741940 		.div_reg = CM_TSENSDIV,
18751941 		.int_bits = 5,
18761942 		.frac_bits = 0),
18771943 	[BCM2835_CLOCK_TEC]	= REGISTER_OSC_CLK(
1944
+		SOC_ALL,
18781945 		.name = "tec",
18791946 		.ctl_reg = CM_TECCTL,
18801947 		.div_reg = CM_TECDIV,
....@@ -1883,6 +1950,7 @@
18831950 
18841951 	/* clocks with vpu parent mux */
18851952 	[BCM2835_CLOCK_H264]	= REGISTER_VPU_CLK(
1953
+		SOC_ALL,
18861954 		.name = "h264",
18871955 		.ctl_reg = CM_H264CTL,
18881956 		.div_reg = CM_H264DIV,
....@@ -1890,6 +1958,7 @@
18901958 		.frac_bits = 8,
18911959 		.tcnt_mux = 1),
18921960 	[BCM2835_CLOCK_ISP]	= REGISTER_VPU_CLK(
1961
+		SOC_ALL,
18931962 		.name = "isp",
18941963 		.ctl_reg = CM_ISPCTL,
18951964 		.div_reg = CM_ISPDIV,
....@@ -1902,6 +1971,7 @@
19021971 	 * in the SDRAM controller can't be used.
19031972 	 */
19041973 	[BCM2835_CLOCK_SDRAM]	= REGISTER_VPU_CLK(
1974
+		SOC_ALL,
19051975 		.name = "sdram",
19061976 		.ctl_reg = CM_SDCCTL,
19071977 		.div_reg = CM_SDCDIV,
....@@ -1909,6 +1979,7 @@
19091979 		.frac_bits = 0,
19101980 		.tcnt_mux = 3),
19111981 	[BCM2835_CLOCK_V3D]	= REGISTER_VPU_CLK(
1982
+		SOC_ALL,
19121983 		.name = "v3d",
19131984 		.ctl_reg = CM_V3DCTL,
19141985 		.div_reg = CM_V3DDIV,
....@@ -1922,6 +1993,7 @@
19221993 	 * in various hardware documentation.
19231994 	 */
19241995 	[BCM2835_CLOCK_VPU]	= REGISTER_VPU_CLK(
1996
+		SOC_ALL,
19251997 		.name = "vpu",
19261998 		.ctl_reg = CM_VPUCTL,
19271999 		.div_reg = CM_VPUDIV,
....@@ -1933,6 +2005,7 @@
19332005 
19342006 	/* clocks with per parent mux */
19352007 	[BCM2835_CLOCK_AVEO]	= REGISTER_PER_CLK(
2008
+		SOC_ALL,
19362009 		.name = "aveo",
19372010 		.ctl_reg = CM_AVEOCTL,
19382011 		.div_reg = CM_AVEODIV,
....@@ -1940,6 +2013,7 @@
19402013 		.frac_bits = 0,
19412014 		.tcnt_mux = 38),
19422015 	[BCM2835_CLOCK_CAM0]	= REGISTER_PER_CLK(
2016
+		SOC_ALL,
19432017 		.name = "cam0",
19442018 		.ctl_reg = CM_CAM0CTL,
19452019 		.div_reg = CM_CAM0DIV,
....@@ -1947,6 +2021,7 @@
19472021 		.frac_bits = 8,
19482022 		.tcnt_mux = 14),
19492023 	[BCM2835_CLOCK_CAM1]	= REGISTER_PER_CLK(
2024
+		SOC_ALL,
19502025 		.name = "cam1",
19512026 		.ctl_reg = CM_CAM1CTL,
19522027 		.div_reg = CM_CAM1DIV,
....@@ -1954,12 +2029,14 @@
19542029 		.frac_bits = 8,
19552030 		.tcnt_mux = 15),
19562031 	[BCM2835_CLOCK_DFT]	= REGISTER_PER_CLK(
2032
+		SOC_ALL,
19572033 		.name = "dft",
19582034 		.ctl_reg = CM_DFTCTL,
19592035 		.div_reg = CM_DFTDIV,
19602036 		.int_bits = 5,
19612037 		.frac_bits = 0),
19622038 	[BCM2835_CLOCK_DPI]	= REGISTER_PER_CLK(
2039
+		SOC_ALL,
19632040 		.name = "dpi",
19642041 		.ctl_reg = CM_DPICTL,
19652042 		.div_reg = CM_DPIDIV,
....@@ -1969,6 +2046,7 @@
19692046 
19702047 	/* Arasan EMMC clock */
19712048 	[BCM2835_CLOCK_EMMC]	= REGISTER_PER_CLK(
2049
+		SOC_ALL,
19722050 		.name = "emmc",
19732051 		.ctl_reg = CM_EMMCCTL,
19742052 		.div_reg = CM_EMMCDIV,
....@@ -1976,8 +2054,19 @@
19762054 		.frac_bits = 8,
19772055 		.tcnt_mux = 39),
19782056 
2057
+	/* EMMC2 clock (only available for BCM2711) */
2058
+	[BCM2711_CLOCK_EMMC2]	= REGISTER_PER_CLK(
2059
+		SOC_BCM2711,
2060
+		.name = "emmc2",
2061
+		.ctl_reg = CM_EMMC2CTL,
2062
+		.div_reg = CM_EMMC2DIV,
2063
+		.int_bits = 4,
2064
+		.frac_bits = 8,
2065
+		.tcnt_mux = 42),
2066
+
19792067 	/* General purpose (GPIO) clocks */
19802068 	[BCM2835_CLOCK_GP0]	= REGISTER_PER_CLK(
2069
+		SOC_ALL,
19812070 		.name = "gp0",
19822071 		.ctl_reg = CM_GP0CTL,
19832072 		.div_reg = CM_GP0DIV,
....@@ -1986,6 +2075,7 @@
19862075 		.is_mash_clock = true,
19872076 		.tcnt_mux = 20),
19882077 	[BCM2835_CLOCK_GP1]	= REGISTER_PER_CLK(
2078
+		SOC_ALL,
19892079 		.name = "gp1",
19902080 		.ctl_reg = CM_GP1CTL,
19912081 		.div_reg = CM_GP1DIV,
....@@ -1995,6 +2085,7 @@
19952085 		.is_mash_clock = true,
19962086 		.tcnt_mux = 21),
19972087 	[BCM2835_CLOCK_GP2]	= REGISTER_PER_CLK(
2088
+		SOC_ALL,
19982089 		.name = "gp2",
19992090 		.ctl_reg = CM_GP2CTL,
20002091 		.div_reg = CM_GP2DIV,
....@@ -2004,6 +2095,7 @@
20042095 
20052096 	/* HDMI state machine */
20062097 	[BCM2835_CLOCK_HSM]	= REGISTER_PER_CLK(
2098
+		SOC_ALL,
20072099 		.name = "hsm",
20082100 		.ctl_reg = CM_HSMCTL,
20092101 		.div_reg = CM_HSMDIV,
....@@ -2011,6 +2103,7 @@
20112103 		.frac_bits = 8,
20122104 		.tcnt_mux = 22),
20132105 	[BCM2835_CLOCK_PCM]	= REGISTER_PCM_CLK(
2106
+		SOC_ALL,
20142107 		.name = "pcm",
20152108 		.ctl_reg = CM_PCMCTL,
20162109 		.div_reg = CM_PCMDIV,
....@@ -2020,6 +2113,7 @@
20202113 		.low_jitter = true,
20212114 		.tcnt_mux = 23),
20222115 	[BCM2835_CLOCK_PWM]	= REGISTER_PER_CLK(
2116
+		SOC_ALL,
20232117 		.name = "pwm",
20242118 		.ctl_reg = CM_PWMCTL,
20252119 		.div_reg = CM_PWMDIV,
....@@ -2028,6 +2122,7 @@
20282122 		.is_mash_clock = true,
20292123 		.tcnt_mux = 24),
20302124 	[BCM2835_CLOCK_SLIM]	= REGISTER_PER_CLK(
2125
+		SOC_ALL,
20312126 		.name = "slim",
20322127 		.ctl_reg = CM_SLIMCTL,
20332128 		.div_reg = CM_SLIMDIV,
....@@ -2036,6 +2131,7 @@
20362131 		.is_mash_clock = true,
20372132 		.tcnt_mux = 25),
20382133 	[BCM2835_CLOCK_SMI]	= REGISTER_PER_CLK(
2134
+		SOC_ALL,
20392135 		.name = "smi",
20402136 		.ctl_reg = CM_SMICTL,
20412137 		.div_reg = CM_SMIDIV,
....@@ -2043,6 +2139,7 @@
20432139 		.frac_bits = 8,
20442140 		.tcnt_mux = 27),
20452141 	[BCM2835_CLOCK_UART]	= REGISTER_PER_CLK(
2142
+		SOC_ALL,
20462143 		.name = "uart",
20472144 		.ctl_reg = CM_UARTCTL,
20482145 		.div_reg = CM_UARTDIV,
....@@ -2052,6 +2149,7 @@
20522149 
20532150 	/* TV encoder clock.  Only operating frequency is 108Mhz.  */
20542151 	[BCM2835_CLOCK_VEC]	= REGISTER_PER_CLK(
2152
+		SOC_ALL,
20552153 		.name = "vec",
20562154 		.ctl_reg = CM_VECCTL,
20572155 		.div_reg = CM_VECDIV,
....@@ -2066,6 +2164,7 @@
20662164 
20672165 	/* dsi clocks */
20682166 	[BCM2835_CLOCK_DSI0E]	= REGISTER_PER_CLK(
2167
+		SOC_ALL,
20692168 		.name = "dsi0e",
20702169 		.ctl_reg = CM_DSI0ECTL,
20712170 		.div_reg = CM_DSI0EDIV,
....@@ -2073,6 +2172,7 @@
20732172 		.frac_bits = 8,
20742173 		.tcnt_mux = 18),
20752174 	[BCM2835_CLOCK_DSI1E]	= REGISTER_PER_CLK(
2175
+		SOC_ALL,
20762176 		.name = "dsi1e",
20772177 		.ctl_reg = CM_DSI1ECTL,
20782178 		.div_reg = CM_DSI1EDIV,
....@@ -2080,6 +2180,7 @@
20802180 		.frac_bits = 8,
20812181 		.tcnt_mux = 19),
20822182 	[BCM2835_CLOCK_DSI0P]	= REGISTER_DSI0_CLK(
2183
+		SOC_ALL,
20832184 		.name = "dsi0p",
20842185 		.ctl_reg = CM_DSI0PCTL,
20852186 		.div_reg = CM_DSI0PDIV,
....@@ -2087,6 +2188,7 @@
20872188 		.frac_bits = 0,
20882189 		.tcnt_mux = 12),
20892190 	[BCM2835_CLOCK_DSI1P]	= REGISTER_DSI1_CLK(
2191
+		SOC_ALL,
20902192 		.name = "dsi1p",
20912193 		.ctl_reg = CM_DSI1PCTL,
20922194 		.div_reg = CM_DSI1PDIV,
....@@ -2103,6 +2205,7 @@
21032205 	 * non-stop vpu clock.
21042206 	 */
21052207 	[BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
2208
+		SOC_ALL,
21062209 		.name = "peri_image",
21072210 		.parent = "vpu",
21082211 		.ctl_reg = CM_PERIICTL),
....@@ -2132,11 +2235,15 @@
21322235 	struct device *dev = &pdev->dev;
21332236 	struct clk_hw **hws;
21342237 	struct bcm2835_cprman *cprman;
2135
-	struct resource *res;
21362238 	const struct bcm2835_clk_desc *desc;
21372239 	const size_t asize = ARRAY_SIZE(clk_desc_array);
2240
+	const struct cprman_plat_data *pdata;
21382241 	size_t i;
21392242 	int ret;
2243
+
2244
+	pdata = of_device_get_match_data(&pdev->dev);
2245
+	if (!pdata)
2246
+		return -ENODEV;
21402247 
21412248 	cprman = devm_kzalloc(dev,
21422249 			      struct_size(cprman, onecell.hws, asize),
....@@ -2146,8 +2253,7 @@
21462253 
21472254 	spin_lock_init(&cprman->regs_lock);
21482255 	cprman->dev = dev;
2149
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2150
-	cprman->regs = devm_ioremap_resource(dev, res);
2256
+	cprman->regs = devm_platform_ioremap_resource(pdev, 0);
21512257 	if (IS_ERR(cprman->regs))
21522258 		return PTR_ERR(cprman->regs);
21532259 
....@@ -2169,12 +2275,15 @@
21692275 	platform_set_drvdata(pdev, cprman);
21702276 
21712277 	cprman->onecell.num = asize;
2278
+	cprman->soc = pdata->soc;
21722279 	hws = cprman->onecell.hws;
21732280 
21742281 	for (i = 0; i < asize; i++) {
21752282 		desc = &clk_desc_array[i];
2176
-		if (desc->clk_register && desc->data)
2283
+		if (desc->clk_register && desc->data &&
2284
+		    (desc->supported & pdata->soc)) {
21772285 			hws[i] = desc->clk_register(cprman, desc->data);
2286
+		}
21782287 	}
21792288 
21802289 	ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
....@@ -2185,8 +2294,17 @@
21852294 				      &cprman->onecell);
21862295 }
21872296 
2297
+static const struct cprman_plat_data cprman_bcm2835_plat_data = {
2298
+	.soc = SOC_BCM2835,
2299
+};
2300
+
2301
+static const struct cprman_plat_data cprman_bcm2711_plat_data = {
2302
+	.soc = SOC_BCM2711,
2303
+};
2304
+
21882305 static const struct of_device_id bcm2835_clk_of_match[] = {
2189
-	{ .compatible = "brcm,bcm2835-cprman", },
2306
+	{ .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2307
+	{ .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
21902308 	{}
21912309 };
21922310 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
....@@ -2203,4 +2321,4 @@
22032321 
22042322 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
22052323 MODULE_DESCRIPTION("BCM2835 clock driver");
2206
-MODULE_LICENSE("GPL v2");
2324
+MODULE_LICENSE("GPL");