add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/clk/at91/clk-utmi.c
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@@ -1,11 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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  */
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5
 
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 #include <linux/clk-provider.h>
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@@ -126,12 +121,14 @@
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 };
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122
 
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 static struct clk_hw * __init
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-at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
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-		       const char *name, const char *parent_name)
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+at91_clk_register_utmi_internal(struct regmap *regmap_pmc,
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+				struct regmap *regmap_sfr,
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+				const char *name, const char *parent_name,
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+				const struct clk_ops *ops, unsigned long flags)
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 {
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 	struct clk_utmi *utmi;
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 	struct clk_hw *hw;
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	int ret;
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 	utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
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@@ -139,10 +136,10 @@
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 		return ERR_PTR(-ENOMEM);
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 	init.name = name;
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-	init.ops = &utmi_ops;
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+	init.ops = ops;
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 	init.parent_names = parent_name ? &parent_name : NULL;
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 	init.num_parents = parent_name ? 1 : 0;
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-	init.flags = CLK_SET_RATE_GATE;
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+	init.flags = flags;
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143
 
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 	utmi->hw.init = &init;
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 	utmi->regmap_pmc = regmap_pmc;
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@@ -158,45 +155,93 @@
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 	return hw;
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 }
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157
 
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-static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
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+struct clk_hw * __init
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+at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
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+		       const char *name, const char *parent_name)
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 {
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-	struct clk_hw *hw;
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-	const char *parent_name;
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-	const char *name = np->name;
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-	struct regmap *regmap_pmc, *regmap_sfr;
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+	return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name,
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+			parent_name, &utmi_ops, CLK_SET_RATE_GATE);
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+}
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165
 
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-	parent_name = of_clk_get_parent_name(np, 0);
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+static int clk_utmi_sama7g5_prepare(struct clk_hw *hw)
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+{
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+	struct clk_utmi *utmi = to_clk_utmi(hw);
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+	struct clk_hw *hw_parent;
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+	unsigned long parent_rate;
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+	unsigned int val;
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-	of_property_read_string(np, "clock-output-names", &name);
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+	hw_parent = clk_hw_get_parent(hw);
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+	parent_rate = clk_hw_get_rate(hw_parent);
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-	regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
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-	if (IS_ERR(regmap_pmc))
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-		return;
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-
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-	/*
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-	 * If the device supports different mainck rates, this value has to be
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-	 * set in the UTMI Clock Trimming register.
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-	 * - 9x5: mainck supports several rates but it is indicated that a
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-	 *   12 MHz is needed in case of USB.
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-	 * - sama5d3 and sama5d2: mainck supports several rates. Configuring
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-	 *   the FREQ field of the UTMI Clock Trimming register is mandatory.
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-	 * - sama5d4: mainck is at 12 MHz.
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-	 *
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-	 * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
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-	 */
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-	regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
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-	if (IS_ERR(regmap_sfr)) {
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-		regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
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-		if (IS_ERR(regmap_sfr))
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-			regmap_sfr = NULL;
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+	switch (parent_rate) {
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+	case 16000000:
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+		val = 0;
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+		break;
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+	case 20000000:
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+		val = 2;
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+		break;
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+	case 24000000:
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+		val = 3;
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+		break;
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+	case 32000000:
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+		val = 5;
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+		break;
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+	default:
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+		pr_err("UTMICK: unsupported main_xtal rate\n");
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+		return -EINVAL;
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 	}
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-	hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
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-	if (IS_ERR(hw))
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-		return;
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+	regmap_write(utmi->regmap_pmc, AT91_PMC_XTALF, val);
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-	of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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-	return;
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+	return 0;
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+
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 }
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-CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
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-	       of_at91sam9x5_clk_utmi_setup);
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+
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+static int clk_utmi_sama7g5_is_prepared(struct clk_hw *hw)
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+{
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+	struct clk_utmi *utmi = to_clk_utmi(hw);
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+	struct clk_hw *hw_parent;
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+	unsigned long parent_rate;
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+	unsigned int val;
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+
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+	hw_parent = clk_hw_get_parent(hw);
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+	parent_rate = clk_hw_get_rate(hw_parent);
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+
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+	regmap_read(utmi->regmap_pmc, AT91_PMC_XTALF, &val);
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+	switch (val & 0x7) {
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+	case 0:
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+		if (parent_rate == 16000000)
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+			return 1;
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+		break;
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+	case 2:
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+		if (parent_rate == 20000000)
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+			return 1;
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+		break;
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+	case 3:
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+		if (parent_rate == 24000000)
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+			return 1;
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+		break;
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+	case 5:
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+		if (parent_rate == 32000000)
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+			return 1;
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+		break;
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+	default:
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+		break;
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+	}
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+
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+	return 0;
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+}
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+
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+static const struct clk_ops sama7g5_utmi_ops = {
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+	.prepare = clk_utmi_sama7g5_prepare,
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+	.is_prepared = clk_utmi_sama7g5_is_prepared,
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+	.recalc_rate = clk_utmi_recalc_rate,
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+};
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+
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+struct clk_hw * __init
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+at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name,
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+			       const char *parent_name)
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+{
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+	return at91_clk_register_utmi_internal(regmap_pmc, NULL, name,
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+			parent_name, &sama7g5_utmi_ops, 0);
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+}