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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Calxeda Highbank AHCI SATA platform driver |
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3 | 4 | * Copyright 2012 Calxeda, Inc. |
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4 | 5 | * |
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5 | 6 | * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov |
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6 | | - * |
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7 | | - * This program is free software; you can redistribute it and/or modify it |
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8 | | - * under the terms and conditions of the GNU General Public License, |
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9 | | - * version 2, as published by the Free Software Foundation. |
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10 | | - * |
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11 | | - * This program is distributed in the hope it will be useful, but WITHOUT |
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12 | | - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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13 | | - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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14 | | - * more details. |
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15 | | - * |
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16 | | - * You should have received a copy of the GNU General Public License along with |
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17 | | - * this program. If not, see <http://www.gnu.org/licenses/>. |
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18 | 7 | */ |
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19 | 8 | #include <linux/kernel.h> |
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20 | 9 | #include <linux/gfp.h> |
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.. | .. |
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31 | 20 | #include <linux/interrupt.h> |
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32 | 21 | #include <linux/delay.h> |
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33 | 22 | #include <linux/export.h> |
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34 | | -#include <linux/gpio.h> |
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35 | | -#include <linux/of_gpio.h> |
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| 23 | +#include <linux/gpio/consumer.h> |
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36 | 24 | |
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37 | 25 | #include "ahci.h" |
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38 | 26 | |
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.. | .. |
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85 | 73 | /* number of extra clocks that the SGPIO PIC controller expects */ |
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86 | 74 | u32 pre_clocks; |
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87 | 75 | u32 post_clocks; |
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88 | | - unsigned sgpio_gpio[SGPIO_PINS]; |
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| 76 | + struct gpio_desc *sgpio_gpiod[SGPIO_PINS]; |
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89 | 77 | u32 sgpio_pattern; |
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90 | 78 | u32 port_to_sgpio[SGPIO_PORTS]; |
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91 | 79 | }; |
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.. | .. |
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131 | 119 | */ |
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132 | 120 | static void ecx_led_cycle_clock(struct ecx_plat_data *pdata) |
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133 | 121 | { |
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134 | | - gpio_set_value(pdata->sgpio_gpio[SCLOCK], 1); |
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| 122 | + gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 1); |
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135 | 123 | udelay(50); |
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136 | | - gpio_set_value(pdata->sgpio_gpio[SCLOCK], 0); |
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| 124 | + gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 0); |
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137 | 125 | udelay(50); |
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138 | 126 | } |
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139 | 127 | |
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.. | .. |
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164 | 152 | for (i = 0; i < pdata->pre_clocks; i++) |
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165 | 153 | ecx_led_cycle_clock(pdata); |
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166 | 154 | |
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167 | | - gpio_set_value(pdata->sgpio_gpio[SLOAD], 1); |
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| 155 | + gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 1); |
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168 | 156 | ecx_led_cycle_clock(pdata); |
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169 | | - gpio_set_value(pdata->sgpio_gpio[SLOAD], 0); |
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| 157 | + gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 0); |
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170 | 158 | /* |
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171 | 159 | * bit-bang out the SGPIO pattern, by consuming a bit and then |
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172 | 160 | * clocking it out. |
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173 | 161 | */ |
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174 | 162 | for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) { |
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175 | | - gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1); |
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| 163 | + gpiod_set_value(pdata->sgpio_gpiod[SDATA], sgpio_out & 1); |
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176 | 164 | sgpio_out >>= 1; |
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177 | 165 | ecx_led_cycle_clock(pdata); |
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178 | 166 | } |
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.. | .. |
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193 | 181 | struct device_node *np = dev->of_node; |
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194 | 182 | struct ecx_plat_data *pdata = hpriv->plat_data; |
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195 | 183 | int i; |
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196 | | - int err; |
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197 | 184 | |
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198 | 185 | for (i = 0; i < SGPIO_PINS; i++) { |
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199 | | - err = of_get_named_gpio(np, "calxeda,sgpio-gpio", i); |
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200 | | - if (err < 0) |
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201 | | - return; |
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| 186 | + struct gpio_desc *gpiod; |
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202 | 187 | |
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203 | | - pdata->sgpio_gpio[i] = err; |
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204 | | - err = gpio_request(pdata->sgpio_gpio[i], "CX SGPIO"); |
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205 | | - if (err) { |
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206 | | - pr_err("sata_highbank gpio_request %d failed: %d\n", |
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207 | | - i, err); |
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208 | | - return; |
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| 188 | + gpiod = devm_gpiod_get_index(dev, "calxeda,sgpio", i, |
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| 189 | + GPIOD_OUT_HIGH); |
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| 190 | + if (IS_ERR(gpiod)) { |
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| 191 | + dev_err(dev, "failed to get GPIO %d\n", i); |
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| 192 | + continue; |
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209 | 193 | } |
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210 | | - gpio_direction_output(pdata->sgpio_gpio[i], 1); |
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| 194 | + gpiod_set_consumer_name(gpiod, "CX SGPIO"); |
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| 195 | + |
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| 196 | + pdata->sgpio_gpiod[i] = gpiod; |
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211 | 197 | } |
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212 | 198 | of_property_read_u32_array(np, "calxeda,led-order", |
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213 | 199 | pdata->port_to_sgpio, |
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.. | .. |
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587 | 573 | struct ahci_host_priv *hpriv = host->private_data; |
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588 | 574 | void __iomem *mmio = hpriv->mmio; |
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589 | 575 | u32 ctl; |
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590 | | - int rc; |
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591 | 576 | |
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592 | 577 | if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { |
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593 | 578 | dev_err(dev, "firmware update required for suspend/resume\n"); |
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.. | .. |
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604 | 589 | writel(ctl, mmio + HOST_CTL); |
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605 | 590 | readl(mmio + HOST_CTL); /* flush */ |
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606 | 591 | |
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607 | | - rc = ata_host_suspend(host, PMSG_SUSPEND); |
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608 | | - if (rc) |
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609 | | - return rc; |
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610 | | - |
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611 | | - return 0; |
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| 592 | + return ata_host_suspend(host, PMSG_SUSPEND); |
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612 | 593 | } |
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613 | 594 | |
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614 | 595 | static int ahci_highbank_resume(struct device *dev) |
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