add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/drivers/ata/ahci_sunxi.c
..
..
@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  * Allwinner sunxi AHCI SATA platform driver
3
4
  * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
..
..
@@ -6,15 +7,6 @@
6
7
  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
7
8
  * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
8
9
  * Daniel Wang <danielwang@allwinnertech.com>
9
- *
10
- * This program is free software; you can redistribute it and/or modify it
11
- * under the terms and conditions of the GNU General Public License,
12
- * version 2, as published by the Free Software Foundation.
13
- *
14
- * This program is distributed in the hope it will be useful, but WITHOUT
15
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17
- * more details.
18
10
  */
19
11
 
20
12
 #include <linux/ahci_platform.h>
..
..
@@ -157,8 +149,51 @@
157
149
 	void __iomem *port_mmio = ahci_port_base(ap);
158
150
 	struct ahci_host_priv *hpriv = ap->host->private_data;
159
151
 
160
-	/* Setup DMA before DMA start */
161
-	sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
152
+	/* Setup DMA before DMA start
153
+	 *
154
+	 * NOTE: A similar SoC with SATA/AHCI by Texas Instruments documents
155
+	 *   this Vendor Specific Port (P0DMACR, aka PxDMACR) in its
156
+	 *   User's Guide document (TMS320C674x/OMAP-L1x Processor
157
+	 *   Serial ATA (SATA) Controller, Literature Number: SPRUGJ8C,
158
+	 *   March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR),
159
+	 *   p.68, https://www.ti.com/lit/ug/sprugj8c/sprugj8c.pdf)
160
+	 *   as equivalent to the following struct:
161
+	 *
162
+	 *   struct AHCI_P0DMACR_t
163
+	 *   {
164
+	 *     unsigned TXTS     : 4;
165
+	 *     unsigned RXTS     : 4;
166
+	 *     unsigned TXABL    : 4;
167
+	 *     unsigned RXABL    : 4;
168
+	 *     unsigned Reserved : 16;
169
+	 *   };
170
+	 *
171
+	 *   TXTS: Transmit Transaction Size (TX_TRANSACTION_SIZE).
172
+	 *     This field defines the DMA transaction size in DWORDs for
173
+	 *     transmit (system bus read, device write) operation. [...]
174
+	 *
175
+	 *   RXTS: Receive Transaction Size (RX_TRANSACTION_SIZE).
176
+	 *     This field defines the Port DMA transaction size in DWORDs
177
+	 *     for receive (system bus write, device read) operation. [...]
178
+	 *
179
+	 *   TXABL: Transmit Burst Limit.
180
+	 *     This field allows software to limit the VBUSP master read
181
+	 *     burst size. [...]
182
+	 *
183
+	 *   RXABL: Receive Burst Limit.
184
+	 *     Allows software to limit the VBUSP master write burst
185
+	 *     size. [...]
186
+	 *
187
+	 *   Reserved: Reserved.
188
+	 *
189
+	 *
190
+	 * NOTE: According to the above document, the following alternative
191
+	 *   to the code below could perhaps be a better option
192
+	 *   (or preparation) for possible further improvements later:
193
+	 *     sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff,
194
+	 *		0x00000033);
195
+	 */
196
+	sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433);
162
197
 
163
198
 	/* Start DMA */
164
199
 	sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
..
..
@@ -181,7 +216,7 @@
181
216
 	struct ahci_host_priv *hpriv;
182
217
 	int rc;
183
218
 
184
-	hpriv = ahci_platform_get_resources(pdev, 0);
219
+	hpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);
185
220
 	if (IS_ERR(hpriv))
186
221
 		return PTR_ERR(hpriv);
187
222
 
..
..
@@ -250,6 +285,7 @@
250
285
 
251
286
 static const struct of_device_id ahci_sunxi_of_match[] = {
252
287
 	{ .compatible = "allwinner,sun4i-a10-ahci", },
288
+	{ .compatible = "allwinner,sun8i-r40-ahci", },
253
289
 	{ },
254
290
 };
255
291
 MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);