hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/x86/kernel/cpu/centaur.c
....@@ -3,6 +3,7 @@
33 #include <linux/sched.h>
44 #include <linux/sched/clock.h>
55
6
+#include <asm/cpu.h>
67 #include <asm/cpufeature.h>
78 #include <asm/e820/api.h>
89 #include <asm/mtrr.h>
....@@ -17,13 +18,6 @@
1718 #define RNG_PRESENT (1 << 2)
1819 #define RNG_ENABLED (1 << 3)
1920 #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
20
-
21
-#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
22
-#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
23
-#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
24
-#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
25
-#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
26
-#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
2721
2822 static void init_c3(struct cpuinfo_x86 *c)
2923 {
....@@ -72,7 +66,8 @@
7266 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
7367 }
7468
75
- cpu_detect_cache_sizes(c);
69
+ if (c->x86 >= 7)
70
+ set_cpu_cap(c, X86_FEATURE_REP_GOOD);
7671 }
7772
7873 enum {
....@@ -98,49 +93,21 @@
9893
9994 static void early_init_centaur(struct cpuinfo_x86 *c)
10095 {
101
- switch (c->x86) {
10296 #ifdef CONFIG_X86_32
103
- case 5:
104
- /* Emulate MTRRs using Centaur's MCR. */
97
+ /* Emulate MTRRs using Centaur's MCR. */
98
+ if (c->x86 == 5)
10599 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
106
- break;
107100 #endif
108
- case 6:
109
- if (c->x86_model >= 0xf)
110
- set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
111
- break;
112
- }
101
+ if ((c->x86 == 6 && c->x86_model >= 0xf) ||
102
+ (c->x86 >= 7))
103
+ set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
104
+
113105 #ifdef CONFIG_X86_64
114106 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
115107 #endif
116108 if (c->x86_power & (1 << 8)) {
117109 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
118110 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
119
- }
120
-}
121
-
122
-static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
123
-{
124
- u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
125
-
126
- rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
127
- msr_ctl = vmx_msr_high | vmx_msr_low;
128
-
129
- if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
130
- set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
131
- if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
132
- set_cpu_cap(c, X86_FEATURE_VNMI);
133
- if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
134
- rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
135
- vmx_msr_low, vmx_msr_high);
136
- msr_ctl2 = vmx_msr_high | vmx_msr_low;
137
- if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
138
- (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
139
- set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
140
- if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
141
- set_cpu_cap(c, X86_FEATURE_EPT);
142
- if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
143
- set_cpu_cap(c, X86_FEATURE_VPID);
144111 }
145112 }
146113
....@@ -178,9 +145,8 @@
178145 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
179146 }
180147
181
- switch (c->x86) {
182148 #ifdef CONFIG_X86_32
183
- case 5:
149
+ if (c->x86 == 5) {
184150 switch (c->x86_model) {
185151 case 4:
186152 name = "C6";
....@@ -240,18 +206,15 @@
240206 c->x86_cache_size = (cc>>24)+(dd>>24);
241207 }
242208 sprintf(c->x86_model_id, "WinChip %s", name);
243
- break;
244
-#endif
245
- case 6:
246
- init_c3(c);
247
- break;
248209 }
210
+#endif
211
+ if (c->x86 == 6 || c->x86 >= 7)
212
+ init_c3(c);
249213 #ifdef CONFIG_X86_64
250214 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
251215 #endif
252216
253
- if (cpu_has(c, X86_FEATURE_VMX))
254
- centaur_detect_vmx_virtcap(c);
217
+ init_ia32_feat_ctl(c);
255218 }
256219
257220 #ifdef CONFIG_X86_32