forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/x86/include/asm/msr-index.h
....@@ -41,12 +41,18 @@
4141 
4242 /* Intel MSRs. Some also available on other CPUs */
4343 
44
+#define MSR_TEST_CTRL				0x00000033
45
+#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT	29
46
+#define MSR_TEST_CTRL_SPLIT_LOCK_DETECT		BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
47
+
4448 #define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */
4549 #define SPEC_CTRL_IBRS			BIT(0)	   /* Indirect Branch Restricted Speculation */
4650 #define SPEC_CTRL_STIBP_SHIFT		1	   /* Single Thread Indirect Branch Predictor (STIBP) bit */
4751 #define SPEC_CTRL_STIBP			BIT(SPEC_CTRL_STIBP_SHIFT)	/* STIBP mask */
4852 #define SPEC_CTRL_SSBD_SHIFT		2	   /* Speculative Store Bypass Disable bit */
4953 #define SPEC_CTRL_SSBD			BIT(SPEC_CTRL_SSBD_SHIFT)	/* Speculative Store Bypass Disable */
54
+#define SPEC_CTRL_RRSBA_DIS_S_SHIFT	6	   /* Disable RRSBA behavior */
55
+#define SPEC_CTRL_RRSBA_DIS_S		BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
5056 
5157 #define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */
5258 #define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */
....@@ -61,6 +67,20 @@
6167 #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT	31
6268 #define MSR_PLATFORM_INFO_CPUID_FAULT		BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
6369 
70
+#define MSR_IA32_UMWAIT_CONTROL			0xe1
71
+#define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE	BIT(0)
72
+#define MSR_IA32_UMWAIT_CONTROL_RESERVED	BIT(1)
73
+/*
74
+ * The time field is bit[31:2], but representing a 32bit value with
75
+ * bit[1:0] zero.
76
+ */
77
+#define MSR_IA32_UMWAIT_CONTROL_TIME_MASK	(~0x03U)
78
+
79
+/* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
80
+#define MSR_IA32_CORE_CAPS			  0x000000cf
81
+#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT  5
82
+#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT	  BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
83
+
6484 #define MSR_PKG_CST_CONFIG_CONTROL	0x000000e2
6585 #define NHM_C3_AUTO_DEMOTE		(1UL << 25)
6686 #define NHM_C1_AUTO_DEMOTE		(1UL << 26)
....@@ -73,6 +93,7 @@
7393 #define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
7494 #define ARCH_CAP_RDCL_NO		BIT(0)	/* Not susceptible to Meltdown */
7595 #define ARCH_CAP_IBRS_ALL		BIT(1)	/* Enhanced IBRS support */
96
+#define ARCH_CAP_RSBA			BIT(2)	/* RET may use alternative branch predictors */
7697 #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH	BIT(3)	/* Skip L1D flush on vmentry */
7798 #define ARCH_CAP_SSB_NO			BIT(4)	/*
7899 						 * Not susceptible to Speculative Store Bypass
....@@ -96,6 +117,41 @@
96117 						 * Not susceptible to
97118 						 * TSX Async Abort (TAA) vulnerabilities.
98119 						 */
120
+#define ARCH_CAP_SBDR_SSDP_NO		BIT(13)	/*
121
+						 * Not susceptible to SBDR and SSDP
122
+						 * variants of Processor MMIO stale data
123
+						 * vulnerabilities.
124
+						 */
125
+#define ARCH_CAP_FBSDP_NO		BIT(14)	/*
126
+						 * Not susceptible to FBSDP variant of
127
+						 * Processor MMIO stale data
128
+						 * vulnerabilities.
129
+						 */
130
+#define ARCH_CAP_PSDP_NO		BIT(15)	/*
131
+						 * Not susceptible to PSDP variant of
132
+						 * Processor MMIO stale data
133
+						 * vulnerabilities.
134
+						 */
135
+#define ARCH_CAP_FB_CLEAR		BIT(17)	/*
136
+						 * VERW clears CPU fill buffer
137
+						 * even on MDS_NO CPUs.
138
+						 */
139
+#define ARCH_CAP_FB_CLEAR_CTRL		BIT(18)	/*
140
+						 * MSR_IA32_MCU_OPT_CTRL[FB_CLEAR_DIS]
141
+						 * bit available to control VERW
142
+						 * behavior.
143
+						 */
144
+#define ARCH_CAP_RRSBA			BIT(19)	/*
145
+						 * Indicates RET may use predictors
146
+						 * other than the RSB. With eIBRS
147
+						 * enabled predictions in kernel mode
148
+						 * are restricted to targets in
149
+						 * kernel.
150
+						 */
151
+#define ARCH_CAP_PBRSB_NO		BIT(24)	/*
152
+						 * Not susceptible to Post-Barrier
153
+						 * Return Stack Buffer Predictions.
154
+						 */
99155 
100156 #define MSR_IA32_FLUSH_CMD		0x0000010b
101157 #define L1D_FLUSH			BIT(0)	/*
....@@ -113,6 +169,7 @@
113169 /* SRBDS support */
114170 #define MSR_IA32_MCU_OPT_CTRL		0x00000123
115171 #define RNGDS_MITG_DIS			BIT(0)
172
+#define FB_CLEAR_DIS			BIT(3)	/* CPU Fill buffer clear disable */
116173 
117174 #define MSR_IA32_SYSENTER_CS		0x00000174
118175 #define MSR_IA32_SYSENTER_ESP		0x00000175
....@@ -131,6 +188,10 @@
131188 
132189 #define MSR_LBR_SELECT			0x000001c8
133190 #define MSR_LBR_TOS			0x000001c9
191
+
192
+#define MSR_IA32_POWER_CTL		0x000001fc
193
+#define MSR_IA32_POWER_CTL_BIT_EE	19
194
+
134195 #define MSR_LBR_NHM_FROM		0x00000680
135196 #define MSR_LBR_NHM_TO			0x000006c0
136197 #define MSR_LBR_CORE_FROM		0x00000040
....@@ -140,15 +201,68 @@
140201 #define LBR_INFO_MISPRED		BIT_ULL(63)
141202 #define LBR_INFO_IN_TX			BIT_ULL(62)
142203 #define LBR_INFO_ABORT			BIT_ULL(61)
204
+#define LBR_INFO_CYC_CNT_VALID		BIT_ULL(60)
143205 #define LBR_INFO_CYCLES			0xffff
206
+#define LBR_INFO_BR_TYPE_OFFSET		56
207
+#define LBR_INFO_BR_TYPE		(0xfull << LBR_INFO_BR_TYPE_OFFSET)
208
+
209
+#define MSR_ARCH_LBR_CTL		0x000014ce
210
+#define ARCH_LBR_CTL_LBREN		BIT(0)
211
+#define ARCH_LBR_CTL_CPL_OFFSET		1
212
+#define ARCH_LBR_CTL_CPL		(0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
213
+#define ARCH_LBR_CTL_STACK_OFFSET	3
214
+#define ARCH_LBR_CTL_STACK		(0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
215
+#define ARCH_LBR_CTL_FILTER_OFFSET	16
216
+#define ARCH_LBR_CTL_FILTER		(0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
217
+#define MSR_ARCH_LBR_DEPTH		0x000014cf
218
+#define MSR_ARCH_LBR_FROM_0		0x00001500
219
+#define MSR_ARCH_LBR_TO_0		0x00001600
220
+#define MSR_ARCH_LBR_INFO_0		0x00001200
144221 
145222 #define MSR_IA32_PEBS_ENABLE		0x000003f1
223
+#define MSR_PEBS_DATA_CFG		0x000003f2
146224 #define MSR_IA32_DS_AREA		0x00000600
147225 #define MSR_IA32_PERF_CAPABILITIES	0x00000345
148226 #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
149227 
150228 #define MSR_IA32_RTIT_CTL		0x00000570
229
+#define RTIT_CTL_TRACEEN		BIT(0)
230
+#define RTIT_CTL_CYCLEACC		BIT(1)
231
+#define RTIT_CTL_OS			BIT(2)
232
+#define RTIT_CTL_USR			BIT(3)
233
+#define RTIT_CTL_PWR_EVT_EN		BIT(4)
234
+#define RTIT_CTL_FUP_ON_PTW		BIT(5)
235
+#define RTIT_CTL_FABRIC_EN		BIT(6)
236
+#define RTIT_CTL_CR3EN			BIT(7)
237
+#define RTIT_CTL_TOPA			BIT(8)
238
+#define RTIT_CTL_MTC_EN			BIT(9)
239
+#define RTIT_CTL_TSC_EN			BIT(10)
240
+#define RTIT_CTL_DISRETC		BIT(11)
241
+#define RTIT_CTL_PTW_EN			BIT(12)
242
+#define RTIT_CTL_BRANCH_EN		BIT(13)
243
+#define RTIT_CTL_MTC_RANGE_OFFSET	14
244
+#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
245
+#define RTIT_CTL_CYC_THRESH_OFFSET	19
246
+#define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
247
+#define RTIT_CTL_PSB_FREQ_OFFSET	24
248
+#define RTIT_CTL_PSB_FREQ		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
249
+#define RTIT_CTL_ADDR0_OFFSET		32
250
+#define RTIT_CTL_ADDR0			(0x0full << RTIT_CTL_ADDR0_OFFSET)
251
+#define RTIT_CTL_ADDR1_OFFSET		36
252
+#define RTIT_CTL_ADDR1			(0x0full << RTIT_CTL_ADDR1_OFFSET)
253
+#define RTIT_CTL_ADDR2_OFFSET		40
254
+#define RTIT_CTL_ADDR2			(0x0full << RTIT_CTL_ADDR2_OFFSET)
255
+#define RTIT_CTL_ADDR3_OFFSET		44
256
+#define RTIT_CTL_ADDR3			(0x0full << RTIT_CTL_ADDR3_OFFSET)
151257 #define MSR_IA32_RTIT_STATUS		0x00000571
258
+#define RTIT_STATUS_FILTEREN		BIT(0)
259
+#define RTIT_STATUS_CONTEXTEN		BIT(1)
260
+#define RTIT_STATUS_TRIGGEREN		BIT(2)
261
+#define RTIT_STATUS_BUFFOVF		BIT(3)
262
+#define RTIT_STATUS_ERROR		BIT(4)
263
+#define RTIT_STATUS_STOPPED		BIT(5)
264
+#define RTIT_STATUS_BYTECNT_OFFSET	32
265
+#define RTIT_STATUS_BYTECNT		(0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
152266 #define MSR_IA32_RTIT_ADDR0_A		0x00000580
153267 #define MSR_IA32_RTIT_ADDR0_B		0x00000581
154268 #define MSR_IA32_RTIT_ADDR1_A		0x00000582
....@@ -182,6 +296,9 @@
182296 #define MSR_IA32_LASTINTFROMIP		0x000001dd
183297 #define MSR_IA32_LASTINTTOIP		0x000001de
184298 
299
+#define MSR_IA32_PASID			0x00000d93
300
+#define MSR_IA32_PASID_VALID		BIT_ULL(31)
301
+
185302 /* DEBUGCTLMSR bits (others vary by model): */
186303 #define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
187304 #define DEBUGCTLMSR_BTF_SHIFT		1
....@@ -192,12 +309,11 @@
192309 #define DEBUGCTLMSR_BTS_OFF_OS		(1UL <<  9)
193310 #define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
194311 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
312
+#define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI	(1UL << 12)
195313 #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT	14
196314 #define DEBUGCTLMSR_FREEZE_IN_SMM	(1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
197315 
198316 #define MSR_PEBS_FRONTEND		0x000003f7
199
-
200
-#define MSR_IA32_POWER_CTL		0x000001fc
201317 
202318 #define MSR_IA32_MC0_CTL		0x00000400
203319 #define MSR_IA32_MC0_STATUS		0x00000401
....@@ -248,6 +364,9 @@
248364 #define MSR_PP1_POWER_LIMIT		0x00000640
249365 #define MSR_PP1_ENERGY_STATUS		0x00000641
250366 #define MSR_PP1_POLICY			0x00000642
367
+
368
+#define MSR_AMD_PKG_ENERGY_STATUS	0xc001029b
369
+#define MSR_AMD_RAPL_POWER_UNIT		0xc0010299
251370 
252371 /* Config TDP MSRs */
253372 #define MSR_CONFIG_TDP_NOMINAL		0x00000648
....@@ -348,18 +467,33 @@
348467 /* Alternative perfctr range with full access. */
349468 #define MSR_IA32_PMC0			0x000004c1
350469 
351
-/* AMD64 MSRs. Not complete. See the architecture manual for a more
352
-   complete list. */
470
+/* Auto-reload via MSR instead of DS area */
471
+#define MSR_RELOAD_PMC0			0x000014c1
472
+#define MSR_RELOAD_FIXED_CTR0		0x00001309
353473 
474
+/*
475
+ * AMD64 MSRs. Not complete. See the architecture manual for a more
476
+ * complete list.
477
+ */
354478 #define MSR_AMD64_PATCH_LEVEL		0x0000008b
355479 #define MSR_AMD64_TSC_RATIO		0xc0000104
356480 #define MSR_AMD64_NB_CFG		0xc001001f
357
-#define MSR_AMD64_CPUID_FN_1		0xc0011004
358481 #define MSR_AMD64_PATCH_LOADER		0xc0010020
482
+#define MSR_AMD_PERF_CTL		0xc0010062
483
+#define MSR_AMD_PERF_STATUS		0xc0010063
484
+#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064
359485 #define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140
360486 #define MSR_AMD64_OSVW_STATUS		0xc0010141
487
+#define MSR_AMD_PPIN_CTL		0xc00102f0
488
+#define MSR_AMD_PPIN			0xc00102f1
489
+#define MSR_AMD64_CPUID_FN_1		0xc0011004
361490 #define MSR_AMD64_LS_CFG		0xc0011020
362491 #define MSR_AMD64_DC_CFG		0xc0011022
492
+
493
+#define MSR_AMD64_DE_CFG		0xc0011029
494
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT	 1
495
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE	BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
496
+
363497 #define MSR_AMD64_BU_CFG2		0xc001102a
364498 #define MSR_AMD64_IBSFETCHCTL		0xc0011030
365499 #define MSR_AMD64_IBSFETCHLINAD		0xc0011031
....@@ -380,14 +514,20 @@
380514 #define MSR_AMD64_ICIBSEXTDCTL		0xc001103c
381515 #define MSR_AMD64_IBSOPDATA4		0xc001103d
382516 #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
517
+#define MSR_AMD64_SEV_ES_GHCB		0xc0010130
383518 #define MSR_AMD64_SEV			0xc0010131
384519 #define MSR_AMD64_SEV_ENABLED_BIT	0
520
+#define MSR_AMD64_SEV_ES_ENABLED_BIT	1
385521 #define MSR_AMD64_SEV_ENABLED		BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
522
+#define MSR_AMD64_SEV_ES_ENABLED	BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
386523 
387524 #define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f
388525 
389526 /* Fam 17h MSRs */
390527 #define MSR_F17H_IRPERF			0xc00000e9
528
+
529
+#define MSR_ZEN2_SPECTRAL_CHICKEN	0xc00110e3
530
+#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT	BIT_ULL(1)
391531 
392532 /* Fam 16h MSRs */
393533 #define MSR_F16H_L2I_PERF_CTL		0xc0010230
....@@ -398,6 +538,8 @@
398538 #define MSR_F16H_DR0_ADDR_MASK		0xc0011027
399539 
400540 /* Fam 15h MSRs */
541
+#define MSR_F15H_CU_PWR_ACCUMULATOR     0xc001007a
542
+#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
401543 #define MSR_F15H_PERF_CTL		0xc0010200
402544 #define MSR_F15H_PERF_CTL0		MSR_F15H_PERF_CTL
403545 #define MSR_F15H_PERF_CTL1		(MSR_F15H_PERF_CTL + 2)
....@@ -428,9 +570,6 @@
428570 #define FAM10H_MMIO_CONF_BASE_MASK	0xfffffffULL
429571 #define FAM10H_MMIO_CONF_BASE_SHIFT	20
430572 #define MSR_FAM10H_NODE_ID		0xc001100c
431
-#define MSR_F10H_DECFG			0xc0011029
432
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT	1
433
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE		BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
434573 
435574 /* K8 MSRs */
436575 #define MSR_K8_TOP_MEM1			0xc001001a
....@@ -508,18 +647,20 @@
508647 #define MSR_IA32_EBL_CR_POWERON		0x0000002a
509648 #define MSR_EBC_FREQUENCY_ID		0x0000002c
510649 #define MSR_SMI_COUNT			0x00000034
511
-#define MSR_IA32_FEATURE_CONTROL        0x0000003a
650
+
651
+/* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
652
+#define MSR_IA32_FEAT_CTL		0x0000003a
653
+#define FEAT_CTL_LOCKED				BIT(0)
654
+#define FEAT_CTL_VMX_ENABLED_INSIDE_SMX		BIT(1)
655
+#define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX	BIT(2)
656
+#define FEAT_CTL_LMCE_ENABLED			BIT(20)
657
+
512658 #define MSR_IA32_TSC_ADJUST             0x0000003b
513659 #define MSR_IA32_BNDCFGS		0x00000d90
514660 
515661 #define MSR_IA32_BNDCFGS_RSVD		0x00000ffc
516662 
517663 #define MSR_IA32_XSS			0x00000da0
518
-
519
-#define FEATURE_CONTROL_LOCKED				(1<<0)
520
-#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
521
-#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)
522
-#define FEATURE_CONTROL_LMCE				(1<<20)
523664 
524665 #define MSR_IA32_APICBASE		0x0000001b
525666 #define MSR_IA32_APICBASE_BSP		(1<<8)
....@@ -537,9 +678,6 @@
537678 #define MSR_IA32_PERF_STATUS		0x00000198
538679 #define MSR_IA32_PERF_CTL		0x00000199
539680 #define INTEL_PERF_CTL_MASK		0xffff
540
-#define MSR_AMD_PSTATE_DEF_BASE		0xc0010064
541
-#define MSR_AMD_PERF_STATUS		0xc0010063
542
-#define MSR_AMD_PERF_CTL		0xc0010062
543681 
544682 #define MSR_IA32_MPERF			0x000000e7
545683 #define MSR_IA32_APERF			0x000000e8
....@@ -770,10 +908,21 @@
770908 #define MSR_CORE_PERF_FIXED_CTR0	0x00000309
771909 #define MSR_CORE_PERF_FIXED_CTR1	0x0000030a
772910 #define MSR_CORE_PERF_FIXED_CTR2	0x0000030b
911
+#define MSR_CORE_PERF_FIXED_CTR3	0x0000030c
773912 #define MSR_CORE_PERF_FIXED_CTR_CTRL	0x0000038d
774913 #define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e
775914 #define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
776915 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390
916
+
917
+#define MSR_PERF_METRICS		0x00000329
918
+
919
+/* PERF_GLOBAL_OVF_CTL bits */
920
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT	55
921
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI		(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
922
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT		62
923
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF			(1ULL <<  MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
924
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT		63
925
+#define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD			(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
777926 
778927 /* Geode defined MSRs */
779928 #define MSR_GEODE_BUSCONT_CONF0		0x00001900
....@@ -808,6 +957,7 @@
808957 #define VMX_BASIC_INOUT		0x0040000000000000LLU
809958 
810959 /* MSR_IA32_VMX_MISC bits */
960
+#define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)
811961 #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
812962 #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE   0x1F
813963 /* AMD-V MSRs */