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2 | 2 | #ifndef _ASM_X86_INTEL_SCU_IPC_H_ |
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3 | 3 | #define _ASM_X86_INTEL_SCU_IPC_H_ |
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4 | 4 | |
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5 | | -#include <linux/notifier.h> |
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| 5 | +#include <linux/ioport.h> |
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6 | 6 | |
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7 | | -#define IPCMSG_INDIRECT_READ 0x02 |
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8 | | -#define IPCMSG_INDIRECT_WRITE 0x05 |
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| 7 | +struct device; |
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| 8 | +struct intel_scu_ipc_dev; |
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9 | 9 | |
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10 | | -#define IPCMSG_COLD_OFF 0x80 /* Only for Tangier */ |
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| 10 | +/** |
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| 11 | + * struct intel_scu_ipc_data - Data used to configure SCU IPC |
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| 12 | + * @mem: Base address of SCU IPC MMIO registers |
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| 13 | + * @irq: The IRQ number used for SCU (optional) |
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| 14 | + */ |
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| 15 | +struct intel_scu_ipc_data { |
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| 16 | + struct resource mem; |
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| 17 | + int irq; |
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| 18 | +}; |
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11 | 19 | |
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12 | | -#define IPCMSG_WARM_RESET 0xF0 |
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13 | | -#define IPCMSG_COLD_RESET 0xF1 |
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14 | | -#define IPCMSG_SOFT_RESET 0xF2 |
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15 | | -#define IPCMSG_COLD_BOOT 0xF3 |
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| 20 | +struct intel_scu_ipc_dev * |
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| 21 | +__intel_scu_ipc_register(struct device *parent, |
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| 22 | + const struct intel_scu_ipc_data *scu_data, |
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| 23 | + struct module *owner); |
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16 | 24 | |
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17 | | -#define IPCMSG_VRTC 0xFA /* Set vRTC device */ |
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18 | | - /* Command id associated with message IPCMSG_VRTC */ |
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19 | | - #define IPC_CMD_VRTC_SETTIME 1 /* Set time */ |
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20 | | - #define IPC_CMD_VRTC_SETALARM 2 /* Set alarm */ |
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| 25 | +#define intel_scu_ipc_register(parent, scu_data) \ |
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| 26 | + __intel_scu_ipc_register(parent, scu_data, THIS_MODULE) |
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21 | 27 | |
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22 | | -/* Read single register */ |
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23 | | -int intel_scu_ipc_ioread8(u16 addr, u8 *data); |
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| 28 | +void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu); |
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24 | 29 | |
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25 | | -/* Read two sequential registers */ |
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26 | | -int intel_scu_ipc_ioread16(u16 addr, u16 *data); |
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| 30 | +struct intel_scu_ipc_dev * |
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| 31 | +__devm_intel_scu_ipc_register(struct device *parent, |
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| 32 | + const struct intel_scu_ipc_data *scu_data, |
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| 33 | + struct module *owner); |
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27 | 34 | |
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28 | | -/* Read four sequential registers */ |
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29 | | -int intel_scu_ipc_ioread32(u16 addr, u32 *data); |
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| 35 | +#define devm_intel_scu_ipc_register(parent, scu_data) \ |
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| 36 | + __devm_intel_scu_ipc_register(parent, scu_data, THIS_MODULE) |
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30 | 37 | |
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31 | | -/* Read a vector */ |
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32 | | -int intel_scu_ipc_readv(u16 *addr, u8 *data, int len); |
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| 38 | +struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void); |
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| 39 | +void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu); |
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| 40 | +struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev); |
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33 | 41 | |
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34 | | -/* Write single register */ |
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35 | | -int intel_scu_ipc_iowrite8(u16 addr, u8 data); |
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| 42 | +int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr, |
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| 43 | + u8 *data); |
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| 44 | +int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr, |
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| 45 | + u8 data); |
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| 46 | +int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr, |
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| 47 | + u8 *data, size_t len); |
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| 48 | +int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr, |
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| 49 | + u8 *data, size_t len); |
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36 | 50 | |
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37 | | -/* Write two sequential registers */ |
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38 | | -int intel_scu_ipc_iowrite16(u16 addr, u16 data); |
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| 51 | +int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr, |
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| 52 | + u8 data, u8 mask); |
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39 | 53 | |
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40 | | -/* Write four sequential registers */ |
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41 | | -int intel_scu_ipc_iowrite32(u16 addr, u32 data); |
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| 54 | +int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd, |
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| 55 | + int sub); |
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| 56 | +int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd, |
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| 57 | + int sub, const void *in, size_t inlen, |
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| 58 | + size_t size, void *out, size_t outlen); |
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42 | 59 | |
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43 | | -/* Write a vector */ |
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44 | | -int intel_scu_ipc_writev(u16 *addr, u8 *data, int len); |
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45 | | - |
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46 | | -/* Update single register based on the mask */ |
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47 | | -int intel_scu_ipc_update_register(u16 addr, u8 data, u8 mask); |
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48 | | - |
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49 | | -/* Issue commands to the SCU with or without data */ |
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50 | | -int intel_scu_ipc_simple_command(int cmd, int sub); |
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51 | | -int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen, |
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52 | | - u32 *out, int outlen); |
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53 | | -int intel_scu_ipc_raw_command(int cmd, int sub, u8 *in, int inlen, |
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54 | | - u32 *out, int outlen, u32 dptr, u32 sptr); |
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55 | | - |
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56 | | -/* I2C control api */ |
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57 | | -int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data); |
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58 | | - |
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59 | | -/* Update FW version */ |
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60 | | -int intel_scu_ipc_fw_update(u8 *buffer, u32 length); |
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61 | | - |
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62 | | -extern struct blocking_notifier_head intel_scu_notifier; |
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63 | | - |
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64 | | -static inline void intel_scu_notifier_add(struct notifier_block *nb) |
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| 60 | +static inline int intel_scu_ipc_dev_command(struct intel_scu_ipc_dev *scu, int cmd, |
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| 61 | + int sub, const void *in, size_t inlen, |
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| 62 | + void *out, size_t outlen) |
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65 | 63 | { |
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66 | | - blocking_notifier_chain_register(&intel_scu_notifier, nb); |
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| 64 | + return intel_scu_ipc_dev_command_with_size(scu, cmd, sub, in, inlen, |
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| 65 | + inlen, out, outlen); |
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67 | 66 | } |
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68 | 67 | |
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69 | | -static inline void intel_scu_notifier_remove(struct notifier_block *nb) |
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70 | | -{ |
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71 | | - blocking_notifier_chain_unregister(&intel_scu_notifier, nb); |
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72 | | -} |
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73 | | - |
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74 | | -static inline int intel_scu_notifier_post(unsigned long v, void *p) |
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75 | | -{ |
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76 | | - return blocking_notifier_call_chain(&intel_scu_notifier, v, p); |
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77 | | -} |
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78 | | - |
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79 | | -#define SCU_AVAILABLE 1 |
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80 | | -#define SCU_DOWN 2 |
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| 68 | +#include <asm/intel_scu_ipc_legacy.h> |
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81 | 69 | |
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82 | 70 | #endif |
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