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2 | 2 | #ifndef _ASM_X86_INTEL_PT_H |
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3 | 3 | #define _ASM_X86_INTEL_PT_H |
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4 | 4 | |
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| 5 | +#define PT_CPUID_LEAVES 2 |
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| 6 | +#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */ |
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| 7 | + |
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| 8 | +enum pt_capabilities { |
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| 9 | + PT_CAP_max_subleaf = 0, |
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| 10 | + PT_CAP_cr3_filtering, |
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| 11 | + PT_CAP_psb_cyc, |
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| 12 | + PT_CAP_ip_filtering, |
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| 13 | + PT_CAP_mtc, |
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| 14 | + PT_CAP_ptwrite, |
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| 15 | + PT_CAP_power_event_trace, |
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| 16 | + PT_CAP_topa_output, |
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| 17 | + PT_CAP_topa_multiple_entries, |
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| 18 | + PT_CAP_single_range_output, |
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| 19 | + PT_CAP_output_subsys, |
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| 20 | + PT_CAP_payloads_lip, |
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| 21 | + PT_CAP_num_address_ranges, |
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| 22 | + PT_CAP_mtc_periods, |
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| 23 | + PT_CAP_cycle_thresholds, |
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| 24 | + PT_CAP_psb_periods, |
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| 25 | +}; |
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| 26 | + |
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5 | 27 | #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) |
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6 | 28 | void cpu_emergency_stop_pt(void); |
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| 29 | +extern u32 intel_pt_validate_hw_cap(enum pt_capabilities cap); |
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| 30 | +extern u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities cap); |
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| 31 | +extern int is_intel_pt_event(struct perf_event *event); |
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7 | 32 | #else |
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8 | 33 | static inline void cpu_emergency_stop_pt(void) {} |
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| 34 | +static inline u32 intel_pt_validate_hw_cap(enum pt_capabilities cap) { return 0; } |
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| 35 | +static inline u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability) { return 0; } |
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| 36 | +static inline int is_intel_pt_event(struct perf_event *event) { return 0; } |
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9 | 37 | #endif |
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10 | 38 | |
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11 | 39 | #endif /* _ASM_X86_INTEL_PT_H */ |
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