hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/x86/include/asm/intel_pt.h
....@@ -2,10 +2,38 @@
22 #ifndef _ASM_X86_INTEL_PT_H
33 #define _ASM_X86_INTEL_PT_H
44
5
+#define PT_CPUID_LEAVES 2
6
+#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */
7
+
8
+enum pt_capabilities {
9
+ PT_CAP_max_subleaf = 0,
10
+ PT_CAP_cr3_filtering,
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+ PT_CAP_psb_cyc,
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+ PT_CAP_ip_filtering,
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+ PT_CAP_mtc,
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+ PT_CAP_ptwrite,
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+ PT_CAP_power_event_trace,
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+ PT_CAP_topa_output,
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+ PT_CAP_topa_multiple_entries,
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+ PT_CAP_single_range_output,
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+ PT_CAP_output_subsys,
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+ PT_CAP_payloads_lip,
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+ PT_CAP_num_address_ranges,
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+ PT_CAP_mtc_periods,
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+ PT_CAP_cycle_thresholds,
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+ PT_CAP_psb_periods,
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+};
26
+
527 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
628 void cpu_emergency_stop_pt(void);
29
+extern u32 intel_pt_validate_hw_cap(enum pt_capabilities cap);
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+extern u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities cap);
31
+extern int is_intel_pt_event(struct perf_event *event);
732 #else
833 static inline void cpu_emergency_stop_pt(void) {}
34
+static inline u32 intel_pt_validate_hw_cap(enum pt_capabilities cap) { return 0; }
35
+static inline u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability) { return 0; }
36
+static inline int is_intel_pt_event(struct perf_event *event) { return 0; }
937 #endif
1038
1139 #endif /* _ASM_X86_INTEL_PT_H */