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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/x86/events/msr.c
....@@ -1,7 +1,9 @@
11 // SPDX-License-Identifier: GPL-2.0
22 #include <linux/perf_event.h>
3
+#include <linux/sysfs.h>
34 #include <linux/nospec.h>
45 #include <asm/intel-family.h>
6
+#include "probe.h"
57 
68 enum perf_msr_id {
79 	PERF_MSR_TSC			= 0,
....@@ -12,32 +14,30 @@
1214 	PERF_MSR_PTSC			= 5,
1315 	PERF_MSR_IRPERF			= 6,
1416 	PERF_MSR_THERM			= 7,
15
-	PERF_MSR_THERM_SNAP		= 8,
16
-	PERF_MSR_THERM_UNIT		= 9,
1717 	PERF_MSR_EVENT_MAX,
1818 };
1919 
20
-static bool test_aperfmperf(int idx)
20
+static bool test_aperfmperf(int idx, void *data)
2121 {
2222 	return boot_cpu_has(X86_FEATURE_APERFMPERF);
2323 }
2424 
25
-static bool test_ptsc(int idx)
25
+static bool test_ptsc(int idx, void *data)
2626 {
2727 	return boot_cpu_has(X86_FEATURE_PTSC);
2828 }
2929 
30
-static bool test_irperf(int idx)
30
+static bool test_irperf(int idx, void *data)
3131 {
3232 	return boot_cpu_has(X86_FEATURE_IRPERF);
3333 }
3434 
35
-static bool test_therm_status(int idx)
35
+static bool test_therm_status(int idx, void *data)
3636 {
3737 	return boot_cpu_has(X86_FEATURE_DTHERM);
3838 }
3939 
40
-static bool test_intel(int idx)
40
+static bool test_intel(int idx, void *data)
4141 {
4242 	if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||
4343 	    boot_cpu_data.x86 != 6)
....@@ -59,24 +59,27 @@
5959 	case INTEL_FAM6_IVYBRIDGE:
6060 	case INTEL_FAM6_IVYBRIDGE_X:
6161 
62
-	case INTEL_FAM6_HASWELL_CORE:
62
+	case INTEL_FAM6_HASWELL:
6363 	case INTEL_FAM6_HASWELL_X:
64
-	case INTEL_FAM6_HASWELL_ULT:
65
-	case INTEL_FAM6_HASWELL_GT3E:
64
+	case INTEL_FAM6_HASWELL_L:
65
+	case INTEL_FAM6_HASWELL_G:
6666 
67
-	case INTEL_FAM6_BROADWELL_CORE:
68
-	case INTEL_FAM6_BROADWELL_XEON_D:
69
-	case INTEL_FAM6_BROADWELL_GT3E:
67
+	case INTEL_FAM6_BROADWELL:
68
+	case INTEL_FAM6_BROADWELL_D:
69
+	case INTEL_FAM6_BROADWELL_G:
7070 	case INTEL_FAM6_BROADWELL_X:
71
+	case INTEL_FAM6_SAPPHIRERAPIDS_X:
7172 
7273 	case INTEL_FAM6_ATOM_SILVERMONT:
73
-	case INTEL_FAM6_ATOM_SILVERMONT_X:
74
+	case INTEL_FAM6_ATOM_SILVERMONT_D:
7475 	case INTEL_FAM6_ATOM_AIRMONT:
7576 
7677 	case INTEL_FAM6_ATOM_GOLDMONT:
77
-	case INTEL_FAM6_ATOM_GOLDMONT_X:
78
-
78
+	case INTEL_FAM6_ATOM_GOLDMONT_D:
7979 	case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
80
+	case INTEL_FAM6_ATOM_TREMONT_D:
81
+	case INTEL_FAM6_ATOM_TREMONT:
82
+	case INTEL_FAM6_ATOM_TREMONT_L:
8083 
8184 	case INTEL_FAM6_XEON_PHI_KNL:
8285 	case INTEL_FAM6_XEON_PHI_KNM:
....@@ -84,12 +87,19 @@
8487 			return true;
8588 		break;
8689 
87
-	case INTEL_FAM6_SKYLAKE_MOBILE:
88
-	case INTEL_FAM6_SKYLAKE_DESKTOP:
90
+	case INTEL_FAM6_SKYLAKE_L:
91
+	case INTEL_FAM6_SKYLAKE:
8992 	case INTEL_FAM6_SKYLAKE_X:
90
-	case INTEL_FAM6_KABYLAKE_MOBILE:
91
-	case INTEL_FAM6_KABYLAKE_DESKTOP:
92
-	case INTEL_FAM6_ICELAKE_MOBILE:
93
+	case INTEL_FAM6_KABYLAKE_L:
94
+	case INTEL_FAM6_KABYLAKE:
95
+	case INTEL_FAM6_COMETLAKE_L:
96
+	case INTEL_FAM6_COMETLAKE:
97
+	case INTEL_FAM6_ICELAKE_L:
98
+	case INTEL_FAM6_ICELAKE:
99
+	case INTEL_FAM6_ICELAKE_X:
100
+	case INTEL_FAM6_ICELAKE_D:
101
+	case INTEL_FAM6_TIGERLAKE_L:
102
+	case INTEL_FAM6_TIGERLAKE:
93103 		if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
94104 			return true;
95105 		break;
....@@ -98,37 +108,51 @@
98108 	return false;
99109 }
100110 
101
-struct perf_msr {
102
-	u64	msr;
103
-	struct	perf_pmu_events_attr *attr;
104
-	bool	(*test)(int idx);
111
+PMU_EVENT_ATTR_STRING(tsc,				attr_tsc,		"event=0x00"	);
112
+PMU_EVENT_ATTR_STRING(aperf,				attr_aperf,		"event=0x01"	);
113
+PMU_EVENT_ATTR_STRING(mperf,				attr_mperf,		"event=0x02"	);
114
+PMU_EVENT_ATTR_STRING(pperf,				attr_pperf,		"event=0x03"	);
115
+PMU_EVENT_ATTR_STRING(smi,				attr_smi,		"event=0x04"	);
116
+PMU_EVENT_ATTR_STRING(ptsc,				attr_ptsc,		"event=0x05"	);
117
+PMU_EVENT_ATTR_STRING(irperf,				attr_irperf,		"event=0x06"	);
118
+PMU_EVENT_ATTR_STRING(cpu_thermal_margin,		attr_therm,		"event=0x07"	);
119
+PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot,	attr_therm_snap,	"1"		);
120
+PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit,		attr_therm_unit,	"C"		);
121
+
122
+static unsigned long msr_mask;
123
+
124
+PMU_EVENT_GROUP(events, aperf);
125
+PMU_EVENT_GROUP(events, mperf);
126
+PMU_EVENT_GROUP(events, pperf);
127
+PMU_EVENT_GROUP(events, smi);
128
+PMU_EVENT_GROUP(events, ptsc);
129
+PMU_EVENT_GROUP(events, irperf);
130
+
131
+static struct attribute *attrs_therm[] = {
132
+	&attr_therm.attr.attr,
133
+	&attr_therm_snap.attr.attr,
134
+	&attr_therm_unit.attr.attr,
135
+	NULL,
105136 };
106137 
107
-PMU_EVENT_ATTR_STRING(tsc,				evattr_tsc,		"event=0x00"	);
108
-PMU_EVENT_ATTR_STRING(aperf,				evattr_aperf,		"event=0x01"	);
109
-PMU_EVENT_ATTR_STRING(mperf,				evattr_mperf,		"event=0x02"	);
110
-PMU_EVENT_ATTR_STRING(pperf,				evattr_pperf,		"event=0x03"	);
111
-PMU_EVENT_ATTR_STRING(smi,				evattr_smi,		"event=0x04"	);
112
-PMU_EVENT_ATTR_STRING(ptsc,				evattr_ptsc,		"event=0x05"	);
113
-PMU_EVENT_ATTR_STRING(irperf,				evattr_irperf,		"event=0x06"	);
114
-PMU_EVENT_ATTR_STRING(cpu_thermal_margin,		evattr_therm,		"event=0x07"	);
115
-PMU_EVENT_ATTR_STRING(cpu_thermal_margin.snapshot,	evattr_therm_snap,	"1"		);
116
-PMU_EVENT_ATTR_STRING(cpu_thermal_margin.unit,		evattr_therm_unit,	"C"		);
138
+static struct attribute_group group_therm = {
139
+	.name  = "events",
140
+	.attrs = attrs_therm,
141
+};
117142 
118143 static struct perf_msr msr[] = {
119
-	[PERF_MSR_TSC]		= { 0,				&evattr_tsc,		NULL,			},
120
-	[PERF_MSR_APERF]	= { MSR_IA32_APERF,		&evattr_aperf,		test_aperfmperf,	},
121
-	[PERF_MSR_MPERF]	= { MSR_IA32_MPERF,		&evattr_mperf,		test_aperfmperf,	},
122
-	[PERF_MSR_PPERF]	= { MSR_PPERF,			&evattr_pperf,		test_intel,		},
123
-	[PERF_MSR_SMI]		= { MSR_SMI_COUNT,		&evattr_smi,		test_intel,		},
124
-	[PERF_MSR_PTSC]		= { MSR_F15H_PTSC,		&evattr_ptsc,		test_ptsc,		},
125
-	[PERF_MSR_IRPERF]	= { MSR_F17H_IRPERF,		&evattr_irperf,		test_irperf,		},
126
-	[PERF_MSR_THERM]	= { MSR_IA32_THERM_STATUS,	&evattr_therm,		test_therm_status,	},
127
-	[PERF_MSR_THERM_SNAP]	= { MSR_IA32_THERM_STATUS,	&evattr_therm_snap,	test_therm_status,	},
128
-	[PERF_MSR_THERM_UNIT]	= { MSR_IA32_THERM_STATUS,	&evattr_therm_unit,	test_therm_status,	},
144
+	[PERF_MSR_TSC]		= { .no_check = true,								},
145
+	[PERF_MSR_APERF]	= { MSR_IA32_APERF,		&group_aperf,		test_aperfmperf,	},
146
+	[PERF_MSR_MPERF]	= { MSR_IA32_MPERF,		&group_mperf,		test_aperfmperf,	},
147
+	[PERF_MSR_PPERF]	= { MSR_PPERF,			&group_pperf,		test_intel,		},
148
+	[PERF_MSR_SMI]		= { MSR_SMI_COUNT,		&group_smi,		test_intel,		},
149
+	[PERF_MSR_PTSC]		= { MSR_F15H_PTSC,		&group_ptsc,		test_ptsc,		},
150
+	[PERF_MSR_IRPERF]	= { MSR_F17H_IRPERF,		&group_irperf,		test_irperf,		},
151
+	[PERF_MSR_THERM]	= { MSR_IA32_THERM_STATUS,	&group_therm,		test_therm_status,	},
129152 };
130153 
131
-static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = {
154
+static struct attribute *events_attrs[] = {
155
+	&attr_tsc.attr.attr,
132156 	NULL,
133157 };
134158 
....@@ -153,6 +177,17 @@
153177 	NULL,
154178 };
155179 
180
+static const struct attribute_group *attr_update[] = {
181
+	&group_aperf,
182
+	&group_mperf,
183
+	&group_pperf,
184
+	&group_smi,
185
+	&group_ptsc,
186
+	&group_irperf,
187
+	&group_therm,
188
+	NULL,
189
+};
190
+
156191 static int msr_event_init(struct perf_event *event)
157192 {
158193 	u64 cfg = event->attr.config;
....@@ -161,13 +196,7 @@
161196 		return -ENOENT;
162197 
163198 	/* unsupported modes and filters */
164
-	if (event->attr.exclude_user   ||
165
-	    event->attr.exclude_kernel ||
166
-	    event->attr.exclude_hv     ||
167
-	    event->attr.exclude_idle   ||
168
-	    event->attr.exclude_host   ||
169
-	    event->attr.exclude_guest  ||
170
-	    event->attr.sample_period) /* no sampling */
199
+	if (event->attr.sample_period) /* no sampling */
171200 		return -EINVAL;
172201 
173202 	if (cfg >= PERF_MSR_EVENT_MAX)
....@@ -175,7 +204,7 @@
175204 
176205 	cfg = array_index_nospec((unsigned long)cfg, PERF_MSR_EVENT_MAX);
177206 
178
-	if (!msr[cfg].attr)
207
+	if (!(msr_mask & (1 << cfg)))
179208 		return -EINVAL;
180209 
181210 	event->hw.idx		= -1;
....@@ -257,33 +286,18 @@
257286 	.start		= msr_event_start,
258287 	.stop		= msr_event_stop,
259288 	.read		= msr_event_update,
260
-	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT,
289
+	.capabilities	= PERF_PMU_CAP_NO_INTERRUPT | PERF_PMU_CAP_NO_EXCLUDE,
290
+	.attr_update	= attr_update,
261291 };
262292 
263293 static int __init msr_init(void)
264294 {
265
-	int i, j = 0;
266
-
267295 	if (!boot_cpu_has(X86_FEATURE_TSC)) {
268296 		pr_cont("no MSR PMU driver.\n");
269297 		return 0;
270298 	}
271299 
272
-	/* Probe the MSRs. */
273
-	for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) {
274
-		u64 val;
275
-
276
-		/* Virt sucks; you cannot tell if a R/O MSR is present :/ */
277
-		if (!msr[i].test(i) || rdmsrl_safe(msr[i].msr, &val))
278
-			msr[i].attr = NULL;
279
-	}
280
-
281
-	/* List remaining MSRs in the sysfs attrs. */
282
-	for (i = 0; i < PERF_MSR_EVENT_MAX; i++) {
283
-		if (msr[i].attr)
284
-			events_attrs[j++] = &msr[i].attr->attr.attr;
285
-	}
286
-	events_attrs[j] = NULL;
300
+	msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL);
287301 
288302 	perf_pmu_register(&pmu_msr, "msr", -1);
289303