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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/x86/events/intel/pt.h
....@@ -1,15 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Intel(R) Processor Trace PMU driver for perf
34  * Copyright (c) 2013-2014, Intel Corporation.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
135  *
146  * Intel PT is specified in the Intel Architecture Instruction Set Extensions
157  * Programming Reference:
....@@ -18,43 +10,6 @@
1810 
1911 #ifndef __INTEL_PT_H__
2012 #define __INTEL_PT_H__
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-
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-/*
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- * PT MSR bit definitions
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- */
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-#define RTIT_CTL_TRACEEN		BIT(0)
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-#define RTIT_CTL_CYCLEACC		BIT(1)
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-#define RTIT_CTL_OS			BIT(2)
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-#define RTIT_CTL_USR			BIT(3)
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-#define RTIT_CTL_PWR_EVT_EN		BIT(4)
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-#define RTIT_CTL_FUP_ON_PTW		BIT(5)
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-#define RTIT_CTL_CR3EN			BIT(7)
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-#define RTIT_CTL_TOPA			BIT(8)
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-#define RTIT_CTL_MTC_EN			BIT(9)
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-#define RTIT_CTL_TSC_EN			BIT(10)
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-#define RTIT_CTL_DISRETC		BIT(11)
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-#define RTIT_CTL_PTW_EN			BIT(12)
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-#define RTIT_CTL_BRANCH_EN		BIT(13)
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-#define RTIT_CTL_MTC_RANGE_OFFSET	14
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-#define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
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-#define RTIT_CTL_CYC_THRESH_OFFSET	19
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-#define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
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-#define RTIT_CTL_PSB_FREQ_OFFSET	24
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-#define RTIT_CTL_PSB_FREQ      		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
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-#define RTIT_CTL_ADDR0_OFFSET		32
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-#define RTIT_CTL_ADDR0      		(0x0full << RTIT_CTL_ADDR0_OFFSET)
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-#define RTIT_CTL_ADDR1_OFFSET		36
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-#define RTIT_CTL_ADDR1      		(0x0full << RTIT_CTL_ADDR1_OFFSET)
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-#define RTIT_CTL_ADDR2_OFFSET		40
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-#define RTIT_CTL_ADDR2      		(0x0full << RTIT_CTL_ADDR2_OFFSET)
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-#define RTIT_CTL_ADDR3_OFFSET		44
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-#define RTIT_CTL_ADDR3      		(0x0full << RTIT_CTL_ADDR3_OFFSET)
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-#define RTIT_STATUS_FILTEREN		BIT(0)
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-#define RTIT_STATUS_CONTEXTEN		BIT(1)
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-#define RTIT_STATUS_TRIGGEREN		BIT(2)
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-#define RTIT_STATUS_BUFFOVF		BIT(3)
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-#define RTIT_STATUS_ERROR		BIT(4)
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-#define RTIT_STATUS_STOPPED		BIT(5)
5813 
5914 /*
6015  * Single-entry ToPA: when this close to region boundary, switch
....@@ -82,29 +37,8 @@
8237 	u64	rsvd4	: 16;
8338 };
8439 
85
-#define PT_CPUID_LEAVES		2
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-#define PT_CPUID_REGS_NUM	4 /* number of regsters (eax, ebx, ecx, edx) */
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-
8840 /* TSC to Core Crystal Clock Ratio */
8941 #define CPUID_TSC_LEAF		0x15
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-
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-enum pt_capabilities {
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-	PT_CAP_max_subleaf = 0,
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-	PT_CAP_cr3_filtering,
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-	PT_CAP_psb_cyc,
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-	PT_CAP_ip_filtering,
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-	PT_CAP_mtc,
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-	PT_CAP_ptwrite,
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-	PT_CAP_power_event_trace,
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-	PT_CAP_topa_output,
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-	PT_CAP_topa_multiple_entries,
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-	PT_CAP_single_range_output,
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-	PT_CAP_payloads_lip,
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-	PT_CAP_num_address_ranges,
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-	PT_CAP_mtc_periods,
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-	PT_CAP_cycle_thresholds,
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-	PT_CAP_psb_periods,
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-};
10842 
10943 struct pt_pmu {
11044 	struct pmu		pmu;
....@@ -119,7 +53,6 @@
11953 /**
12054  * struct pt_buffer - buffer configuration; one buffer per task_struct or
12155  *		cpu, depending on perf event configuration
122
- * @cpu:	cpu for per-cpu allocation
12356  * @tables:	list of ToPA tables in this buffer
12457  * @first:	shorthand for first topa table
12558  * @last:	shorthand for last topa table
....@@ -131,13 +64,15 @@
13164  * @lost:	if data was lost/truncated
13265  * @head:	logical write offset inside the buffer
13366  * @snapshot:	if this is for a snapshot/overwrite counter
134
- * @stop_pos:	STOP topa entry in the buffer
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- * @intr_pos:	INT topa entry in the buffer
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+ * @single:	use Single Range Output instead of ToPA
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+ * @stop_pos:	STOP topa entry index
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+ * @intr_pos:	INT topa entry index
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+ * @stop_te:	STOP topa entry pointer
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+ * @intr_te:	INT topa entry pointer
13672  * @data_pages:	array of pages from perf
13773  * @topa_index:	table of topa entries indexed by page offset
13874  */
13975 struct pt_buffer {
140
-	int			cpu;
14176 	struct list_head	tables;
14277 	struct topa		*first, *last, *cur;
14378 	unsigned int		cur_idx;
....@@ -146,9 +81,10 @@
14681 	local_t			data_size;
14782 	local64_t		head;
14883 	bool			snapshot;
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-	unsigned long		stop_pos, intr_pos;
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+	bool			single;
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+	long			stop_pos, intr_pos;
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+	struct topa_entry	*stop_te, *intr_te;
15087 	void			**data_pages;
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-	struct topa_entry	*topa_index[0];
15288 };
15389 
15490 #define PT_FILTERS_NUM	4
....@@ -177,16 +113,20 @@
177113 
178114 /**
179115  * struct pt - per-cpu pt context
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- * @handle:	perf output handle
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+ * @handle:		perf output handle
181117  * @filters:		last configured filters
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- * @handle_nmi:	do handle PT PMI on this cpu, there's an active event
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- * @vmx_on:	1 if VMX is ON on this cpu
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+ * @handle_nmi:		do handle PT PMI on this cpu, there's an active event
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+ * @vmx_on:		1 if VMX is ON on this cpu
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+ * @output_base:	cached RTIT_OUTPUT_BASE MSR value
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+ * @output_mask:	cached RTIT_OUTPUT_MASK MSR value
184122  */
185123 struct pt {
186124 	struct perf_output_handle handle;
187125 	struct pt_filters	filters;
188126 	int			handle_nmi;
189127 	int			vmx_on;
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+	u64			output_base;
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+	u64			output_mask;
190130 };
191131 
192132 #endif /* __INTEL_PT_H__ */