hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/x86/events/intel/pt.h
....@@ -1,15 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23 * Intel(R) Processor Trace PMU driver for perf
34 * Copyright (c) 2013-2014, Intel Corporation.
4
- *
5
- * This program is free software; you can redistribute it and/or modify it
6
- * under the terms and conditions of the GNU General Public License,
7
- * version 2, as published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope it will be useful, but WITHOUT
10
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12
- * more details.
135 *
146 * Intel PT is specified in the Intel Architecture Instruction Set Extensions
157 * Programming Reference:
....@@ -18,43 +10,6 @@
1810
1911 #ifndef __INTEL_PT_H__
2012 #define __INTEL_PT_H__
21
-
22
-/*
23
- * PT MSR bit definitions
24
- */
25
-#define RTIT_CTL_TRACEEN BIT(0)
26
-#define RTIT_CTL_CYCLEACC BIT(1)
27
-#define RTIT_CTL_OS BIT(2)
28
-#define RTIT_CTL_USR BIT(3)
29
-#define RTIT_CTL_PWR_EVT_EN BIT(4)
30
-#define RTIT_CTL_FUP_ON_PTW BIT(5)
31
-#define RTIT_CTL_CR3EN BIT(7)
32
-#define RTIT_CTL_TOPA BIT(8)
33
-#define RTIT_CTL_MTC_EN BIT(9)
34
-#define RTIT_CTL_TSC_EN BIT(10)
35
-#define RTIT_CTL_DISRETC BIT(11)
36
-#define RTIT_CTL_PTW_EN BIT(12)
37
-#define RTIT_CTL_BRANCH_EN BIT(13)
38
-#define RTIT_CTL_MTC_RANGE_OFFSET 14
39
-#define RTIT_CTL_MTC_RANGE (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
40
-#define RTIT_CTL_CYC_THRESH_OFFSET 19
41
-#define RTIT_CTL_CYC_THRESH (0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
42
-#define RTIT_CTL_PSB_FREQ_OFFSET 24
43
-#define RTIT_CTL_PSB_FREQ (0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
44
-#define RTIT_CTL_ADDR0_OFFSET 32
45
-#define RTIT_CTL_ADDR0 (0x0full << RTIT_CTL_ADDR0_OFFSET)
46
-#define RTIT_CTL_ADDR1_OFFSET 36
47
-#define RTIT_CTL_ADDR1 (0x0full << RTIT_CTL_ADDR1_OFFSET)
48
-#define RTIT_CTL_ADDR2_OFFSET 40
49
-#define RTIT_CTL_ADDR2 (0x0full << RTIT_CTL_ADDR2_OFFSET)
50
-#define RTIT_CTL_ADDR3_OFFSET 44
51
-#define RTIT_CTL_ADDR3 (0x0full << RTIT_CTL_ADDR3_OFFSET)
52
-#define RTIT_STATUS_FILTEREN BIT(0)
53
-#define RTIT_STATUS_CONTEXTEN BIT(1)
54
-#define RTIT_STATUS_TRIGGEREN BIT(2)
55
-#define RTIT_STATUS_BUFFOVF BIT(3)
56
-#define RTIT_STATUS_ERROR BIT(4)
57
-#define RTIT_STATUS_STOPPED BIT(5)
5813
5914 /*
6015 * Single-entry ToPA: when this close to region boundary, switch
....@@ -82,29 +37,8 @@
8237 u64 rsvd4 : 16;
8338 };
8439
85
-#define PT_CPUID_LEAVES 2
86
-#define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */
87
-
8840 /* TSC to Core Crystal Clock Ratio */
8941 #define CPUID_TSC_LEAF 0x15
90
-
91
-enum pt_capabilities {
92
- PT_CAP_max_subleaf = 0,
93
- PT_CAP_cr3_filtering,
94
- PT_CAP_psb_cyc,
95
- PT_CAP_ip_filtering,
96
- PT_CAP_mtc,
97
- PT_CAP_ptwrite,
98
- PT_CAP_power_event_trace,
99
- PT_CAP_topa_output,
100
- PT_CAP_topa_multiple_entries,
101
- PT_CAP_single_range_output,
102
- PT_CAP_payloads_lip,
103
- PT_CAP_num_address_ranges,
104
- PT_CAP_mtc_periods,
105
- PT_CAP_cycle_thresholds,
106
- PT_CAP_psb_periods,
107
-};
10842
10943 struct pt_pmu {
11044 struct pmu pmu;
....@@ -119,7 +53,6 @@
11953 /**
12054 * struct pt_buffer - buffer configuration; one buffer per task_struct or
12155 * cpu, depending on perf event configuration
122
- * @cpu: cpu for per-cpu allocation
12356 * @tables: list of ToPA tables in this buffer
12457 * @first: shorthand for first topa table
12558 * @last: shorthand for last topa table
....@@ -131,13 +64,15 @@
13164 * @lost: if data was lost/truncated
13265 * @head: logical write offset inside the buffer
13366 * @snapshot: if this is for a snapshot/overwrite counter
134
- * @stop_pos: STOP topa entry in the buffer
135
- * @intr_pos: INT topa entry in the buffer
67
+ * @single: use Single Range Output instead of ToPA
68
+ * @stop_pos: STOP topa entry index
69
+ * @intr_pos: INT topa entry index
70
+ * @stop_te: STOP topa entry pointer
71
+ * @intr_te: INT topa entry pointer
13672 * @data_pages: array of pages from perf
13773 * @topa_index: table of topa entries indexed by page offset
13874 */
13975 struct pt_buffer {
140
- int cpu;
14176 struct list_head tables;
14277 struct topa *first, *last, *cur;
14378 unsigned int cur_idx;
....@@ -146,9 +81,10 @@
14681 local_t data_size;
14782 local64_t head;
14883 bool snapshot;
149
- unsigned long stop_pos, intr_pos;
84
+ bool single;
85
+ long stop_pos, intr_pos;
86
+ struct topa_entry *stop_te, *intr_te;
15087 void **data_pages;
151
- struct topa_entry *topa_index[0];
15288 };
15389
15490 #define PT_FILTERS_NUM 4
....@@ -177,16 +113,20 @@
177113
178114 /**
179115 * struct pt - per-cpu pt context
180
- * @handle: perf output handle
116
+ * @handle: perf output handle
181117 * @filters: last configured filters
182
- * @handle_nmi: do handle PT PMI on this cpu, there's an active event
183
- * @vmx_on: 1 if VMX is ON on this cpu
118
+ * @handle_nmi: do handle PT PMI on this cpu, there's an active event
119
+ * @vmx_on: 1 if VMX is ON on this cpu
120
+ * @output_base: cached RTIT_OUTPUT_BASE MSR value
121
+ * @output_mask: cached RTIT_OUTPUT_MASK MSR value
184122 */
185123 struct pt {
186124 struct perf_output_handle handle;
187125 struct pt_filters filters;
188126 int handle_nmi;
189127 int vmx_on;
128
+ u64 output_base;
129
+ u64 output_mask;
190130 };
191131
192132 #endif /* __INTEL_PT_H__ */