add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/s390/include/asm/pci_clp.h
..
..
@@ -7,6 +7,7 @@
7
7
 /*
8
8
  * Call Logical Processor - Command Codes
9
9
  */
10
+#define CLP_SLPC		0x0001
10
11
 #define CLP_LIST_PCI		0x0002
11
12
 #define CLP_QUERY_PCI_FN	0x0003
12
13
 #define CLP_QUERY_PCI_FNGRP	0x0004
..
..
@@ -43,11 +44,26 @@
43
44
 
44
45
 #define CLP_SET_ENABLE_PCI_FN	0	/* Yes, 0 enables it */
45
46
 #define CLP_SET_DISABLE_PCI_FN	1	/* Yes, 1 disables it */
47
+#define CLP_SET_ENABLE_MIO	2
48
+#define CLP_SET_DISABLE_MIO	3
46
49
 
47
50
 #define CLP_UTIL_STR_LEN	64
48
51
 #define CLP_PFIP_NR_SEGMENTS	4
49
52
 
50
53
 extern bool zpci_unique_uid;
54
+
55
+struct clp_rsp_slpc_pci {
56
+	struct clp_rsp_hdr hdr;
57
+	u32 reserved2[4];
58
+	u32 lpif[8];
59
+	u32 reserved3[4];
60
+	u32 vwb		:  1;
61
+	u32		:  1;
62
+	u32 mio_wb	:  6;
63
+	u32		: 24;
64
+	u32 reserved5[3];
65
+	u32 lpic[8];
66
+} __packed;
51
67
 
52
68
 /* List PCI functions request */
53
69
 struct clp_req_list_pci {
..
..
@@ -68,6 +84,17 @@
68
84
 	struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
69
85
 } __packed;
70
86
 
87
+struct mio_info {
88
+	u32 valid : 6;
89
+	u32 : 26;
90
+	u32 : 32;
91
+	struct {
92
+		u64 wb;
93
+		u64 wt;
94
+	} addr[PCI_STD_NUM_BARS];
95
+	u32 reserved[6];
96
+} __packed;
97
+
71
98
 /* Query PCI function request */
72
99
 struct clp_req_query_pci {
73
100
 	struct clp_req_hdr hdr;
..
..
@@ -80,22 +107,32 @@
80
107
 struct clp_rsp_query_pci {
81
108
 	struct clp_rsp_hdr hdr;
82
109
 	u16 vfn;			/* virtual fn number */
83
-	u16			:  7;
110
+	u16			:  3;
111
+	u16 rid_avail		:  1;
112
+	u16 is_physfn		:  1;
113
+	u16 reserved1		:  1;
114
+	u16 mio_addr_avail	:  1;
84
115
 	u16 util_str_avail	:  1;	/* utility string available? */
85
116
 	u16 pfgid		:  8;	/* pci function group id */
86
117
 	u32 fid;			/* pci function id */
87
-	u8 bar_size[PCI_BAR_COUNT];
118
+	u8 bar_size[PCI_STD_NUM_BARS];
88
119
 	u16 pchid;
89
-	__le32 bar[PCI_BAR_COUNT];
120
+	__le32 bar[PCI_STD_NUM_BARS];
90
121
 	u8 pfip[CLP_PFIP_NR_SEGMENTS];	/* pci function internal path */
91
-	u32			: 16;
122
+	u16			: 12;
123
+	u16 port		:  4;
92
124
 	u8 fmb_len;
93
125
 	u8 pft;				/* pci function type */
94
126
 	u64 sdma;			/* start dma as */
95
127
 	u64 edma;			/* end dma as */
96
-	u32 reserved[11];
128
+#define ZPCI_RID_MASK_DEVFN 0x00ff
129
+	u16 rid;			/* BUS/DEVFN PCI address */
130
+	u16 reserved0;
131
+	u32 reserved[10];
97
132
 	u32 uid;			/* user defined id */
98
133
 	u8 util_str[CLP_UTIL_STR_LEN];	/* utility string */
134
+	u32 reserved2[16];
135
+	struct mio_info mio;
99
136
 } __packed;
100
137
 
101
138
 /* Query PCI function group request */
..
..
@@ -118,7 +155,11 @@
118
155
 	u8 refresh		:  1;	/* TLB refresh mode */
119
156
 	u16 reserved2;
120
157
 	u16 mui;
121
-	u64 reserved3;
158
+	u16			: 16;
159
+	u16 maxfaal;
160
+	u16			:  4;
161
+	u16 dnoi		: 12;
162
+	u16 maxcpu;
122
163
 	u64 dasm;			/* dma address space mask */
123
164
 	u64 msia;			/* MSI address */
124
165
 	u64 reserved4;
..
..
@@ -139,11 +180,17 @@
139
180
 struct clp_rsp_set_pci {
140
181
 	struct clp_rsp_hdr hdr;
141
182
 	u32 fh;				/* function handle */
142
-	u32 reserved3;
143
-	u64 reserved4;
183
+	u32 reserved1;
184
+	u64 reserved2;
185
+	struct mio_info mio;
144
186
 } __packed;
145
187
 
146
188
 /* Combined request/response block structures used by clp insn */
189
+struct clp_req_rsp_slpc_pci {
190
+	struct clp_req_slpc request;
191
+	struct clp_rsp_slpc_pci response;
192
+} __packed;
193
+
147
194
 struct clp_req_rsp_list_pci {
148
195
 	struct clp_req_list_pci request;
149
196
 	struct clp_rsp_list_pci response;