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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * SMP initialisation and IPI support |
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3 | 4 | * Based on arch/arm64/kernel/smp.c |
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.. | .. |
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5 | 6 | * Copyright (C) 2012 ARM Ltd. |
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6 | 7 | * Copyright (C) 2015 Regents of the University of California |
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7 | 8 | * Copyright (C) 2017 SiFive |
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8 | | - * |
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9 | | - * This program is free software; you can redistribute it and/or modify |
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10 | | - * it under the terms of the GNU General Public License version 2 as |
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11 | | - * published by the Free Software Foundation. |
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12 | | - * |
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13 | | - * This program is distributed in the hope that it will be useful, |
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14 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | | - * GNU General Public License for more details. |
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17 | 9 | */ |
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18 | 10 | |
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| 11 | +#include <linux/arch_topology.h> |
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19 | 12 | #include <linux/module.h> |
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20 | 13 | #include <linux/init.h> |
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21 | 14 | #include <linux/kernel.h> |
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.. | .. |
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30 | 23 | #include <linux/irq.h> |
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31 | 24 | #include <linux/of.h> |
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32 | 25 | #include <linux/sched/task_stack.h> |
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| 26 | +#include <linux/sched/mm.h> |
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| 27 | +#include <asm/cpu_ops.h> |
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33 | 28 | #include <asm/irq.h> |
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34 | 29 | #include <asm/mmu_context.h> |
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35 | 30 | #include <asm/tlbflush.h> |
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36 | 31 | #include <asm/sections.h> |
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37 | 32 | #include <asm/sbi.h> |
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| 33 | +#include <asm/smp.h> |
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38 | 34 | |
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39 | | -void *__cpu_up_stack_pointer[NR_CPUS]; |
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40 | | -void *__cpu_up_task_pointer[NR_CPUS]; |
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| 35 | +#include "head.h" |
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| 36 | + |
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| 37 | +static DECLARE_COMPLETION(cpu_running); |
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41 | 38 | |
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42 | 39 | void __init smp_prepare_boot_cpu(void) |
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43 | 40 | { |
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| 41 | + init_cpu_topology(); |
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44 | 42 | } |
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45 | 43 | |
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46 | 44 | void __init smp_prepare_cpus(unsigned int max_cpus) |
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47 | 45 | { |
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| 46 | + int cpuid; |
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| 47 | + int ret; |
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| 48 | + |
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| 49 | + store_cpu_topology(smp_processor_id()); |
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| 50 | + |
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| 51 | + /* This covers non-smp usecase mandated by "nosmp" option */ |
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| 52 | + if (max_cpus == 0) |
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| 53 | + return; |
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| 54 | + |
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| 55 | + for_each_possible_cpu(cpuid) { |
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| 56 | + if (cpuid == smp_processor_id()) |
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| 57 | + continue; |
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| 58 | + if (cpu_ops[cpuid]->cpu_prepare) { |
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| 59 | + ret = cpu_ops[cpuid]->cpu_prepare(cpuid); |
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| 60 | + if (ret) |
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| 61 | + continue; |
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| 62 | + } |
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| 63 | + set_cpu_present(cpuid, true); |
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| 64 | + } |
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48 | 65 | } |
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49 | 66 | |
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50 | 67 | void __init setup_smp(void) |
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51 | 68 | { |
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52 | | - struct device_node *dn = NULL; |
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53 | | - int hart, im_okay_therefore_i_am = 0; |
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| 69 | + struct device_node *dn; |
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| 70 | + int hart; |
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| 71 | + bool found_boot_cpu = false; |
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| 72 | + int cpuid = 1; |
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54 | 73 | |
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55 | | - while ((dn = of_find_node_by_type(dn, "cpu"))) { |
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56 | | - hart = riscv_of_processor_hart(dn); |
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57 | | - if (hart >= 0) { |
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58 | | - set_cpu_possible(hart, true); |
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59 | | - set_cpu_present(hart, true); |
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60 | | - if (hart == smp_processor_id()) { |
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61 | | - BUG_ON(im_okay_therefore_i_am); |
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62 | | - im_okay_therefore_i_am = 1; |
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63 | | - } |
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| 74 | + cpu_set_ops(0); |
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| 75 | + |
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| 76 | + for_each_of_cpu_node(dn) { |
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| 77 | + hart = riscv_of_processor_hartid(dn); |
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| 78 | + if (hart < 0) |
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| 79 | + continue; |
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| 80 | + |
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| 81 | + if (hart == cpuid_to_hartid_map(0)) { |
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| 82 | + BUG_ON(found_boot_cpu); |
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| 83 | + found_boot_cpu = 1; |
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| 84 | + continue; |
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64 | 85 | } |
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| 86 | + if (cpuid >= NR_CPUS) { |
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| 87 | + pr_warn("Invalid cpuid [%d] for hartid [%d]\n", |
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| 88 | + cpuid, hart); |
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| 89 | + break; |
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| 90 | + } |
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| 91 | + |
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| 92 | + cpuid_to_hartid_map(cpuid) = hart; |
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| 93 | + cpuid++; |
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65 | 94 | } |
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66 | 95 | |
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67 | | - BUG_ON(!im_okay_therefore_i_am); |
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| 96 | + BUG_ON(!found_boot_cpu); |
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| 97 | + |
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| 98 | + if (cpuid > nr_cpu_ids) |
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| 99 | + pr_warn("Total number of cpus [%d] is greater than nr_cpus option value [%d]\n", |
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| 100 | + cpuid, nr_cpu_ids); |
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| 101 | + |
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| 102 | + for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++) { |
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| 103 | + if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID) { |
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| 104 | + cpu_set_ops(cpuid); |
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| 105 | + set_cpu_possible(cpuid, true); |
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| 106 | + } |
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| 107 | + } |
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| 108 | +} |
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| 109 | + |
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| 110 | +static int start_secondary_cpu(int cpu, struct task_struct *tidle) |
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| 111 | +{ |
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| 112 | + if (cpu_ops[cpu]->cpu_start) |
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| 113 | + return cpu_ops[cpu]->cpu_start(cpu, tidle); |
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| 114 | + |
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| 115 | + return -EOPNOTSUPP; |
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68 | 116 | } |
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69 | 117 | |
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70 | 118 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
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71 | 119 | { |
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| 120 | + int ret = 0; |
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72 | 121 | tidle->thread_info.cpu = cpu; |
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73 | 122 | |
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74 | | - /* |
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75 | | - * On RISC-V systems, all harts boot on their own accord. Our _start |
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76 | | - * selects the first hart to boot the kernel and causes the remainder |
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77 | | - * of the harts to spin in a loop waiting for their stack pointer to be |
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78 | | - * setup by that main hart. Writing __cpu_up_stack_pointer signals to |
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79 | | - * the spinning harts that they can continue the boot process. |
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80 | | - */ |
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81 | | - smp_mb(); |
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82 | | - __cpu_up_stack_pointer[cpu] = task_stack_page(tidle) + THREAD_SIZE; |
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83 | | - __cpu_up_task_pointer[cpu] = tidle; |
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| 123 | + ret = start_secondary_cpu(cpu, tidle); |
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| 124 | + if (!ret) { |
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| 125 | + wait_for_completion_timeout(&cpu_running, |
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| 126 | + msecs_to_jiffies(1000)); |
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84 | 127 | |
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85 | | - while (!cpu_online(cpu)) |
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86 | | - cpu_relax(); |
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| 128 | + if (!cpu_online(cpu)) { |
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| 129 | + pr_crit("CPU%u: failed to come online\n", cpu); |
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| 130 | + ret = -EIO; |
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| 131 | + } |
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| 132 | + } else { |
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| 133 | + pr_crit("CPU%u: failed to start\n", cpu); |
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| 134 | + } |
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87 | 135 | |
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88 | | - return 0; |
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| 136 | + return ret; |
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89 | 137 | } |
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90 | 138 | |
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91 | 139 | void __init smp_cpus_done(unsigned int max_cpus) |
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.. | .. |
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95 | 143 | /* |
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96 | 144 | * C entry point for a secondary processor. |
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97 | 145 | */ |
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98 | | -asmlinkage void __init smp_callin(void) |
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| 146 | +asmlinkage __visible void smp_callin(void) |
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99 | 147 | { |
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100 | 148 | struct mm_struct *mm = &init_mm; |
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| 149 | + unsigned int curr_cpuid = smp_processor_id(); |
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| 150 | + |
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| 151 | + riscv_clear_ipi(); |
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101 | 152 | |
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102 | 153 | /* All kernel threads share the same mm context. */ |
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103 | | - atomic_inc(&mm->mm_count); |
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| 154 | + mmgrab(mm); |
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104 | 155 | current->active_mm = mm; |
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105 | 156 | |
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106 | | - trap_init(); |
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107 | | - notify_cpu_starting(smp_processor_id()); |
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108 | | - set_cpu_online(smp_processor_id(), 1); |
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| 157 | + store_cpu_topology(curr_cpuid); |
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| 158 | + notify_cpu_starting(curr_cpuid); |
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| 159 | + set_cpu_online(curr_cpuid, 1); |
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| 160 | + |
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| 161 | + /* |
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| 162 | + * Remote TLB flushes are ignored while the CPU is offline, so emit |
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| 163 | + * a local TLB flush right now just in case. |
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| 164 | + */ |
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109 | 165 | local_flush_tlb_all(); |
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| 166 | + complete(&cpu_running); |
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| 167 | + /* |
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| 168 | + * Disable preemption before enabling interrupts, so we don't try to |
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| 169 | + * schedule a CPU that hasn't actually started yet. |
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| 170 | + */ |
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110 | 171 | local_irq_enable(); |
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111 | | - preempt_disable(); |
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112 | 172 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
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113 | 173 | } |
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