hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/riscv/kernel/irq.c
....@@ -7,53 +7,18 @@
77
88 #include <linux/interrupt.h>
99 #include <linux/irqchip.h>
10
-#include <linux/irqdomain.h>
10
+#include <linux/seq_file.h>
11
+#include <asm/smp.h>
1112
12
-/*
13
- * Possible interrupt causes:
14
- */
15
-#define INTERRUPT_CAUSE_SOFTWARE 1
16
-#define INTERRUPT_CAUSE_TIMER 5
17
-#define INTERRUPT_CAUSE_EXTERNAL 9
18
-
19
-/*
20
- * The high order bit of the trap cause register is always set for
21
- * interrupts, which allows us to differentiate them from exceptions
22
- * quickly. The INTERRUPT_CAUSE_* macros don't contain that bit, so we
23
- * need to mask it off.
24
- */
25
-#define INTERRUPT_CAUSE_FLAG (1UL << (__riscv_xlen - 1))
26
-
27
-asmlinkage void __irq_entry do_IRQ(struct pt_regs *regs, unsigned long cause)
13
+int arch_show_interrupts(struct seq_file *p, int prec)
2814 {
29
- struct pt_regs *old_regs = set_irq_regs(regs);
30
-
31
- irq_enter();
32
- switch (cause & ~INTERRUPT_CAUSE_FLAG) {
33
- case INTERRUPT_CAUSE_TIMER:
34
- riscv_timer_interrupt();
35
- break;
36
-#ifdef CONFIG_SMP
37
- case INTERRUPT_CAUSE_SOFTWARE:
38
- /*
39
- * We only use software interrupts to pass IPIs, so if a non-SMP
40
- * system gets one, then we don't know what to do.
41
- */
42
- riscv_software_interrupt();
43
- break;
44
-#endif
45
- case INTERRUPT_CAUSE_EXTERNAL:
46
- handle_arch_irq(regs);
47
- break;
48
- default:
49
- panic("unexpected interrupt cause");
50
- }
51
- irq_exit();
52
-
53
- set_irq_regs(old_regs);
15
+ show_ipi_stats(p, prec);
16
+ return 0;
5417 }
5518
5619 void __init init_IRQ(void)
5720 {
5821 irqchip_init();
22
+ if (!handle_arch_irq)
23
+ panic("No interrupt controller found.");
5924 }