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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * Copyright (C) 2012 Regents of the University of California |
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3 | | - * |
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4 | | - * This program is free software; you can redistribute it and/or |
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5 | | - * modify it under the terms of the GNU General Public License |
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6 | | - * as published by the Free Software Foundation, version 2. |
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7 | | - * |
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8 | | - * This program is distributed in the hope that it will be useful, |
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9 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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10 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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11 | | - * GNU General Public License for more details. |
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12 | 4 | */ |
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13 | 5 | |
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14 | 6 | #include <linux/init.h> |
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15 | 7 | #include <linux/seq_file.h> |
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16 | 8 | #include <linux/of.h> |
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| 9 | +#include <asm/smp.h> |
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17 | 10 | |
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18 | | -/* Return -1 if not a valid hart */ |
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19 | | -int riscv_of_processor_hart(struct device_node *node) |
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| 11 | +/* |
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| 12 | + * Returns the hart ID of the given device tree node, or -ENODEV if the node |
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| 13 | + * isn't an enabled and valid RISC-V hart node. |
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| 14 | + */ |
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| 15 | +int riscv_of_processor_hartid(struct device_node *node) |
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20 | 16 | { |
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21 | | - const char *isa, *status; |
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| 17 | + const char *isa; |
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22 | 18 | u32 hart; |
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23 | 19 | |
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24 | 20 | if (!of_device_is_compatible(node, "riscv")) { |
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25 | 21 | pr_warn("Found incompatible CPU\n"); |
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26 | | - return -(ENODEV); |
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| 22 | + return -ENODEV; |
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27 | 23 | } |
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28 | 24 | |
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29 | 25 | if (of_property_read_u32(node, "reg", &hart)) { |
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30 | 26 | pr_warn("Found CPU without hart ID\n"); |
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31 | | - return -(ENODEV); |
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32 | | - } |
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33 | | - if (hart >= NR_CPUS) { |
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34 | | - pr_info("Found hart ID %d, which is above NR_CPUs. Disabling this hart\n", hart); |
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35 | | - return -(ENODEV); |
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| 27 | + return -ENODEV; |
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36 | 28 | } |
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37 | 29 | |
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38 | | - if (of_property_read_string(node, "status", &status)) { |
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39 | | - pr_warn("CPU with hartid=%d has no \"status\" property\n", hart); |
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40 | | - return -(ENODEV); |
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41 | | - } |
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42 | | - if (strcmp(status, "okay")) { |
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43 | | - pr_info("CPU with hartid=%d has a non-okay status of \"%s\"\n", hart, status); |
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44 | | - return -(ENODEV); |
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| 30 | + if (!of_device_is_available(node)) { |
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| 31 | + pr_info("CPU with hartid=%d is not available\n", hart); |
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| 32 | + return -ENODEV; |
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45 | 33 | } |
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46 | 34 | |
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47 | 35 | if (of_property_read_string(node, "riscv,isa", &isa)) { |
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48 | 36 | pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); |
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49 | | - return -(ENODEV); |
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| 37 | + return -ENODEV; |
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50 | 38 | } |
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51 | 39 | if (isa[0] != 'r' || isa[1] != 'v') { |
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52 | 40 | pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); |
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53 | | - return -(ENODEV); |
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| 41 | + return -ENODEV; |
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54 | 42 | } |
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55 | 43 | |
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56 | 44 | return hart; |
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57 | 45 | } |
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58 | 46 | |
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| 47 | +/* |
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| 48 | + * Find hart ID of the CPU DT node under which given DT node falls. |
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| 49 | + * |
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| 50 | + * To achieve this, we walk up the DT tree until we find an active |
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| 51 | + * RISC-V core (HART) node and extract the cpuid from it. |
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| 52 | + */ |
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| 53 | +int riscv_of_parent_hartid(struct device_node *node) |
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| 54 | +{ |
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| 55 | + for (; node; node = node->parent) { |
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| 56 | + if (of_device_is_compatible(node, "riscv")) |
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| 57 | + return riscv_of_processor_hartid(node); |
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| 58 | + } |
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| 59 | + |
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| 60 | + return -1; |
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| 61 | +} |
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| 62 | + |
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59 | 63 | #ifdef CONFIG_PROC_FS |
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| 64 | + |
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| 65 | +static void print_isa(struct seq_file *f, const char *isa) |
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| 66 | +{ |
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| 67 | + /* Print the entire ISA as it is */ |
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| 68 | + seq_puts(f, "isa\t\t: "); |
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| 69 | + seq_write(f, isa, strlen(isa)); |
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| 70 | + seq_puts(f, "\n"); |
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| 71 | +} |
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| 72 | + |
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| 73 | +static void print_mmu(struct seq_file *f, const char *mmu_type) |
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| 74 | +{ |
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| 75 | +#if defined(CONFIG_32BIT) |
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| 76 | + if (strcmp(mmu_type, "riscv,sv32") != 0) |
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| 77 | + return; |
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| 78 | +#elif defined(CONFIG_64BIT) |
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| 79 | + if (strcmp(mmu_type, "riscv,sv39") != 0 && |
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| 80 | + strcmp(mmu_type, "riscv,sv48") != 0) |
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| 81 | + return; |
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| 82 | +#endif |
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| 83 | + |
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| 84 | + seq_printf(f, "mmu\t\t: %s\n", mmu_type+6); |
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| 85 | +} |
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60 | 86 | |
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61 | 87 | static void *c_start(struct seq_file *m, loff_t *pos) |
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62 | 88 | { |
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.. | .. |
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78 | 104 | |
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79 | 105 | static int c_show(struct seq_file *m, void *v) |
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80 | 106 | { |
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81 | | - unsigned long hart_id = (unsigned long)v - 1; |
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82 | | - struct device_node *node = of_get_cpu_node(hart_id, NULL); |
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| 107 | + unsigned long cpu_id = (unsigned long)v - 1; |
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| 108 | + struct device_node *node = of_get_cpu_node(cpu_id, NULL); |
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83 | 109 | const char *compat, *isa, *mmu; |
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84 | 110 | |
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85 | | - seq_printf(m, "hart\t: %lu\n", hart_id); |
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86 | | - if (!of_property_read_string(node, "riscv,isa", &isa) |
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87 | | - && isa[0] == 'r' |
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88 | | - && isa[1] == 'v') |
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89 | | - seq_printf(m, "isa\t: %s\n", isa); |
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90 | | - if (!of_property_read_string(node, "mmu-type", &mmu) |
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91 | | - && !strncmp(mmu, "riscv,", 6)) |
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92 | | - seq_printf(m, "mmu\t: %s\n", mmu+6); |
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| 111 | + seq_printf(m, "processor\t: %lu\n", cpu_id); |
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| 112 | + seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); |
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| 113 | + if (!of_property_read_string(node, "riscv,isa", &isa)) |
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| 114 | + print_isa(m, isa); |
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| 115 | + if (!of_property_read_string(node, "mmu-type", &mmu)) |
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| 116 | + print_mmu(m, mmu); |
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93 | 117 | if (!of_property_read_string(node, "compatible", &compat) |
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94 | 118 | && strcmp(compat, "riscv")) |
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95 | | - seq_printf(m, "uarch\t: %s\n", compat); |
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| 119 | + seq_printf(m, "uarch\t\t: %s\n", compat); |
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96 | 120 | seq_puts(m, "\n"); |
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| 121 | + of_node_put(node); |
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97 | 122 | |
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98 | 123 | return 0; |
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99 | 124 | } |
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