hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/powerpc/platforms/512x/clock-commonclk.c
....@@ -1,14 +1,10 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23 * Copyright (C) 2013 DENX Software Engineering
34 *
45 * Gerhard Sittig, <gsi@denx.de>
56 *
67 * common clock driver support for the MPC512x platform
7
- *
8
- * This is free software; you can redistribute it and/or modify it
9
- * under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
128 */
139
1410 #include <linux/bitops.h>
....@@ -239,6 +235,7 @@
239235 const char *name, const char *parent_name, u8 clkflags,
240236 u32 __iomem *reg, u8 pos, u8 len, int divflags)
241237 {
238
+ divflags |= CLK_DIVIDER_BIG_ENDIAN;
242239 return clk_register_divider(NULL, name, parent_name, clkflags,
243240 reg, pos, len, divflags, &clklock);
244241 }
....@@ -250,7 +247,7 @@
250247 {
251248 u8 divflags;
252249
253
- divflags = 0;
250
+ divflags = CLK_DIVIDER_BIG_ENDIAN;
254251 return clk_register_divider_table(NULL, name, parent_name, 0,
255252 reg, pos, len, divflags,
256253 divtab, &clklock);
....@@ -261,10 +258,12 @@
261258 u32 __iomem *reg, u8 pos)
262259 {
263260 int clkflags;
261
+ u8 gateflags;
264262
265263 clkflags = CLK_SET_RATE_PARENT;
264
+ gateflags = CLK_GATE_BIG_ENDIAN;
266265 return clk_register_gate(NULL, name, parent_name, clkflags,
267
- reg, pos, 0, &clklock);
266
+ reg, pos, gateflags, &clklock);
268267 }
269268
270269 static inline struct clk *mpc512x_clk_muxed(const char *name,
....@@ -275,7 +274,7 @@
275274 u8 muxflags;
276275
277276 clkflags = CLK_SET_RATE_PARENT;
278
- muxflags = 0;
277
+ muxflags = CLK_MUX_BIG_ENDIAN;
279278 return clk_register_mux(NULL, name,
280279 parent_names, parent_count, clkflags,
281280 reg, pos, len, muxflags, &clklock);