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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/powerpc/lib/sstep.c
....@@ -1,12 +1,8 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Single-step support.
34  *
45  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
5
- *
6
- * This program is free software; you can redistribute it and/or
7
- * modify it under the terms of the GNU General Public License
8
- * as published by the Free Software Foundation; either version
9
- * 2 of the License, or (at your option) any later version.
106  */
117 #include <linux/kernel.h>
128 #include <linux/kprobes.h>
....@@ -17,8 +13,10 @@
1713 #include <linux/uaccess.h>
1814 #include <asm/cpu_has_feature.h>
1915 #include <asm/cputable.h>
16
+#include <asm/disassemble.h>
2017 
2118 extern char system_call_common[];
19
+extern char system_call_vectored_emulate[];
2220 
2321 #ifdef CONFIG_PPC64
2422 /* Bits in SRR1 that are copied from MSR */
....@@ -110,11 +108,11 @@
110108 {
111109 	if (!user_mode(regs))
112110 		return 1;
113
-	if (__access_ok(ea, nb, USER_DS))
111
+	if (access_ok((void __user *)ea, nb))
114112 		return 1;
115
-	if (__access_ok(ea, 1, USER_DS))
113
+	if (access_ok((void __user *)ea, 1))
116114 		/* Access overlaps the end of the user region */
117
-		regs->dar = USER_DS.seg;
115
+		regs->dar = TASK_SIZE_MAX - 1;
118116 	else
119117 		regs->dar = ea;
120118 	return 0;
....@@ -187,6 +185,47 @@
187185 	ea = regs->gpr[rb];
188186 	if (ra)
189187 		ea += regs->gpr[ra];
188
+
189
+	return ea;
190
+}
191
+
192
+/*
193
+ * Calculate effective address for a MLS:D-form / 8LS:D-form
194
+ * prefixed instruction
195
+ */
196
+static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
197
+						  unsigned int suffix,
198
+						  const struct pt_regs *regs)
199
+{
200
+	int ra, prefix_r;
201
+	unsigned int  dd;
202
+	unsigned long ea, d0, d1, d;
203
+
204
+	prefix_r = GET_PREFIX_R(instr);
205
+	ra = GET_PREFIX_RA(suffix);
206
+
207
+	d0 = instr & 0x3ffff;
208
+	d1 = suffix & 0xffff;
209
+	d = (d0 << 16) | d1;
210
+
211
+	/*
212
+	 * sign extend a 34 bit number
213
+	 */
214
+	dd = (unsigned int)(d >> 2);
215
+	ea = (signed int)dd;
216
+	ea = (ea << 2) | (d & 0x3);
217
+
218
+	if (!prefix_r && ra)
219
+		ea += regs->gpr[ra];
220
+	else if (!prefix_r && !ra)
221
+		; /* Leave ea as is */
222
+	else if (prefix_r)
223
+		ea += regs->nip;
224
+
225
+	/*
226
+	 * (prefix_r && ra) is an invalid form. Should already be
227
+	 * checked for by caller!
228
+	 */
190229 
191230 	return ea;
192231 }
....@@ -910,7 +949,10 @@
910949 
911950 #define __put_user_asmx(x, addr, err, op, cr)		\
912951 	__asm__ __volatile__(				\
952
+		".machine push\n"			\
953
+		".machine power8\n"			\
913954 		"1:	" op " %2,0,%3\n"		\
955
+		".machine pop\n"			\
914956 		"	mfcr	%1\n"			\
915957 		"2:\n"					\
916958 		".section .fixup,\"ax\"\n"		\
....@@ -923,7 +965,10 @@
923965 
924966 #define __get_user_asmx(x, addr, err, op)		\
925967 	__asm__ __volatile__(				\
968
+		".machine push\n"			\
969
+		".machine power8\n"			\
926970 		"1:	"op" %1,0,%2\n"			\
971
+		".machine pop\n"			\
927972 		"2:\n"					\
928973 		".section .fixup,\"ax\"\n"		\
929974 		"3:	li	%0,%3\n"		\
....@@ -1167,54 +1212,66 @@
11671212  * otherwise.
11681213  */
11691214 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1170
-		  unsigned int instr)
1215
+		  struct ppc_inst instr)
11711216 {
1172
-	unsigned int opcode, ra, rb, rd, spr, u;
1217
+#ifdef CONFIG_PPC64
1218
+	unsigned int suffixopcode, prefixtype, prefix_r;
1219
+#endif
1220
+	unsigned int opcode, ra, rb, rc, rd, spr, u;
11731221 	unsigned long int imm;
11741222 	unsigned long int val, val2;
11751223 	unsigned int mb, me, sh;
1224
+	unsigned int word, suffix;
11761225 	long ival;
1226
+
1227
+	word = ppc_inst_val(instr);
1228
+	suffix = ppc_inst_suffix(instr);
11771229 
11781230 	op->type = COMPUTE;
11791231 
1180
-	opcode = instr >> 26;
1232
+	opcode = ppc_inst_primary_opcode(instr);
11811233 	switch (opcode) {
11821234 	case 16:	/* bc */
11831235 		op->type = BRANCH;
1184
-		imm = (signed short)(instr & 0xfffc);
1185
-		if ((instr & 2) == 0)
1236
+		imm = (signed short)(word & 0xfffc);
1237
+		if ((word & 2) == 0)
11861238 			imm += regs->nip;
11871239 		op->val = truncate_if_32bit(regs->msr, imm);
1188
-		if (instr & 1)
1240
+		if (word & 1)
11891241 			op->type |= SETLK;
1190
-		if (branch_taken(instr, regs, op))
1242
+		if (branch_taken(word, regs, op))
11911243 			op->type |= BRTAKEN;
11921244 		return 1;
11931245 #ifdef CONFIG_PPC64
11941246 	case 17:	/* sc */
1195
-		if ((instr & 0xfe2) == 2)
1247
+		if ((word & 0xfe2) == 2)
11961248 			op->type = SYSCALL;
1197
-		else
1249
+		else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1250
+				(word & 0xfe3) == 1) {	/* scv */
1251
+			op->type = SYSCALL_VECTORED_0;
1252
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
1253
+				goto unknown_opcode;
1254
+		} else
11981255 			op->type = UNKNOWN;
11991256 		return 0;
12001257 #endif
12011258 	case 18:	/* b */
12021259 		op->type = BRANCH | BRTAKEN;
1203
-		imm = instr & 0x03fffffc;
1260
+		imm = word & 0x03fffffc;
12041261 		if (imm & 0x02000000)
12051262 			imm -= 0x04000000;
1206
-		if ((instr & 2) == 0)
1263
+		if ((word & 2) == 0)
12071264 			imm += regs->nip;
12081265 		op->val = truncate_if_32bit(regs->msr, imm);
1209
-		if (instr & 1)
1266
+		if (word & 1)
12101267 			op->type |= SETLK;
12111268 		return 1;
12121269 	case 19:
1213
-		switch ((instr >> 1) & 0x3ff) {
1270
+		switch ((word >> 1) & 0x3ff) {
12141271 		case 0:		/* mcrf */
12151272 			op->type = COMPUTE + SETCC;
1216
-			rd = 7 - ((instr >> 23) & 0x7);
1217
-			ra = 7 - ((instr >> 18) & 0x7);
1273
+			rd = 7 - ((word >> 23) & 0x7);
1274
+			ra = 7 - ((word >> 18) & 0x7);
12181275 			rd *= 4;
12191276 			ra *= 4;
12201277 			val = (regs->ccr >> ra) & 0xf;
....@@ -1224,11 +1281,11 @@
12241281 		case 16:	/* bclr */
12251282 		case 528:	/* bcctr */
12261283 			op->type = BRANCH;
1227
-			imm = (instr & 0x400)? regs->ctr: regs->link;
1284
+			imm = (word & 0x400)? regs->ctr: regs->link;
12281285 			op->val = truncate_if_32bit(regs->msr, imm);
1229
-			if (instr & 1)
1286
+			if (word & 1)
12301287 				op->type |= SETLK;
1231
-			if (branch_taken(instr, regs, op))
1288
+			if (branch_taken(word, regs, op))
12321289 				op->type |= BRTAKEN;
12331290 			return 1;
12341291 
....@@ -1251,23 +1308,23 @@
12511308 		case 417:	/* crorc */
12521309 		case 449:	/* cror */
12531310 			op->type = COMPUTE + SETCC;
1254
-			ra = (instr >> 16) & 0x1f;
1255
-			rb = (instr >> 11) & 0x1f;
1256
-			rd = (instr >> 21) & 0x1f;
1311
+			ra = (word >> 16) & 0x1f;
1312
+			rb = (word >> 11) & 0x1f;
1313
+			rd = (word >> 21) & 0x1f;
12571314 			ra = (regs->ccr >> (31 - ra)) & 1;
12581315 			rb = (regs->ccr >> (31 - rb)) & 1;
1259
-			val = (instr >> (6 + ra * 2 + rb)) & 1;
1316
+			val = (word >> (6 + ra * 2 + rb)) & 1;
12601317 			op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
12611318 				(val << (31 - rd));
12621319 			return 1;
12631320 		}
12641321 		break;
12651322 	case 31:
1266
-		switch ((instr >> 1) & 0x3ff) {
1323
+		switch ((word >> 1) & 0x3ff) {
12671324 		case 598:	/* sync */
12681325 			op->type = BARRIER + BARRIER_SYNC;
12691326 #ifdef __powerpc64__
1270
-			switch ((instr >> 21) & 3) {
1327
+			switch ((word >> 21) & 3) {
12711328 			case 1:		/* lwsync */
12721329 				op->type = BARRIER + BARRIER_LWSYNC;
12731330 				break;
....@@ -1289,33 +1346,94 @@
12891346 	if (!FULL_REGS(regs))
12901347 		return -1;
12911348 
1292
-	rd = (instr >> 21) & 0x1f;
1293
-	ra = (instr >> 16) & 0x1f;
1294
-	rb = (instr >> 11) & 0x1f;
1349
+	rd = (word >> 21) & 0x1f;
1350
+	ra = (word >> 16) & 0x1f;
1351
+	rb = (word >> 11) & 0x1f;
1352
+	rc = (word >> 6) & 0x1f;
12951353 
12961354 	switch (opcode) {
12971355 #ifdef __powerpc64__
1356
+	case 1:
1357
+		if (!cpu_has_feature(CPU_FTR_ARCH_31))
1358
+			goto unknown_opcode;
1359
+
1360
+		prefix_r = GET_PREFIX_R(word);
1361
+		ra = GET_PREFIX_RA(suffix);
1362
+		rd = (suffix >> 21) & 0x1f;
1363
+		op->reg = rd;
1364
+		op->val = regs->gpr[rd];
1365
+		suffixopcode = get_op(suffix);
1366
+		prefixtype = (word >> 24) & 0x3;
1367
+		switch (prefixtype) {
1368
+		case 2:
1369
+			if (prefix_r && ra)
1370
+				return 0;
1371
+			switch (suffixopcode) {
1372
+			case 14:	/* paddi */
1373
+				op->type = COMPUTE | PREFIXED;
1374
+				op->val = mlsd_8lsd_ea(word, suffix, regs);
1375
+				goto compute_done;
1376
+			}
1377
+		}
1378
+		break;
12981379 	case 2:		/* tdi */
1299
-		if (rd & trap_compare(regs->gpr[ra], (short) instr))
1380
+		if (rd & trap_compare(regs->gpr[ra], (short) word))
13001381 			goto trap;
13011382 		return 1;
13021383 #endif
13031384 	case 3:		/* twi */
1304
-		if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1385
+		if (rd & trap_compare((int)regs->gpr[ra], (short) word))
13051386 			goto trap;
13061387 		return 1;
13071388 
1389
+#ifdef __powerpc64__
1390
+	case 4:
1391
+		/*
1392
+		 * There are very many instructions with this primary opcode
1393
+		 * introduced in the ISA as early as v2.03. However, the ones
1394
+		 * we currently emulate were all introduced with ISA 3.0
1395
+		 */
1396
+		if (!cpu_has_feature(CPU_FTR_ARCH_300))
1397
+			goto unknown_opcode;
1398
+
1399
+		switch (word & 0x3f) {
1400
+		case 48:	/* maddhd */
1401
+			asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1402
+				     "=r" (op->val) : "r" (regs->gpr[ra]),
1403
+				     "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1404
+			goto compute_done;
1405
+
1406
+		case 49:	/* maddhdu */
1407
+			asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1408
+				     "=r" (op->val) : "r" (regs->gpr[ra]),
1409
+				     "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1410
+			goto compute_done;
1411
+
1412
+		case 51:	/* maddld */
1413
+			asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1414
+				     "=r" (op->val) : "r" (regs->gpr[ra]),
1415
+				     "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1416
+			goto compute_done;
1417
+		}
1418
+
1419
+		/*
1420
+		 * There are other instructions from ISA 3.0 with the same
1421
+		 * primary opcode which do not have emulation support yet.
1422
+		 */
1423
+		goto unknown_opcode;
1424
+#endif
1425
+
13081426 	case 7:		/* mulli */
1309
-		op->val = regs->gpr[ra] * (short) instr;
1427
+		op->val = regs->gpr[ra] * (short) word;
13101428 		goto compute_done;
13111429 
13121430 	case 8:		/* subfic */
1313
-		imm = (short) instr;
1431
+		imm = (short) word;
13141432 		add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
13151433 		return 1;
13161434 
13171435 	case 10:	/* cmpli */
1318
-		imm = (unsigned short) instr;
1436
+		imm = (unsigned short) word;
13191437 		val = regs->gpr[ra];
13201438 #ifdef __powerpc64__
13211439 		if ((rd & 1) == 0)
....@@ -1325,7 +1443,7 @@
13251443 		return 1;
13261444 
13271445 	case 11:	/* cmpi */
1328
-		imm = (short) instr;
1446
+		imm = (short) word;
13291447 		val = regs->gpr[ra];
13301448 #ifdef __powerpc64__
13311449 		if ((rd & 1) == 0)
....@@ -1335,35 +1453,37 @@
13351453 		return 1;
13361454 
13371455 	case 12:	/* addic */
1338
-		imm = (short) instr;
1456
+		imm = (short) word;
13391457 		add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
13401458 		return 1;
13411459 
13421460 	case 13:	/* addic. */
1343
-		imm = (short) instr;
1461
+		imm = (short) word;
13441462 		add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
13451463 		set_cr0(regs, op);
13461464 		return 1;
13471465 
13481466 	case 14:	/* addi */
1349
-		imm = (short) instr;
1467
+		imm = (short) word;
13501468 		if (ra)
13511469 			imm += regs->gpr[ra];
13521470 		op->val = imm;
13531471 		goto compute_done;
13541472 
13551473 	case 15:	/* addis */
1356
-		imm = ((short) instr) << 16;
1474
+		imm = ((short) word) << 16;
13571475 		if (ra)
13581476 			imm += regs->gpr[ra];
13591477 		op->val = imm;
13601478 		goto compute_done;
13611479 
13621480 	case 19:
1363
-		if (((instr >> 1) & 0x1f) == 2) {
1481
+		if (((word >> 1) & 0x1f) == 2) {
13641482 			/* addpcis */
1365
-			imm = (short) (instr & 0xffc1);	/* d0 + d2 fields */
1366
-			imm |= (instr >> 15) & 0x3e;	/* d1 field */
1483
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
1484
+				goto unknown_opcode;
1485
+			imm = (short) (word & 0xffc1);	/* d0 + d2 fields */
1486
+			imm |= (word >> 15) & 0x3e;	/* d1 field */
13671487 			op->val = regs->nip + (imm << 16) + 4;
13681488 			goto compute_done;
13691489 		}
....@@ -1371,65 +1491,65 @@
13711491 		return 0;
13721492 
13731493 	case 20:	/* rlwimi */
1374
-		mb = (instr >> 6) & 0x1f;
1375
-		me = (instr >> 1) & 0x1f;
1494
+		mb = (word >> 6) & 0x1f;
1495
+		me = (word >> 1) & 0x1f;
13761496 		val = DATA32(regs->gpr[rd]);
13771497 		imm = MASK32(mb, me);
13781498 		op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
13791499 		goto logical_done;
13801500 
13811501 	case 21:	/* rlwinm */
1382
-		mb = (instr >> 6) & 0x1f;
1383
-		me = (instr >> 1) & 0x1f;
1502
+		mb = (word >> 6) & 0x1f;
1503
+		me = (word >> 1) & 0x1f;
13841504 		val = DATA32(regs->gpr[rd]);
13851505 		op->val = ROTATE(val, rb) & MASK32(mb, me);
13861506 		goto logical_done;
13871507 
13881508 	case 23:	/* rlwnm */
1389
-		mb = (instr >> 6) & 0x1f;
1390
-		me = (instr >> 1) & 0x1f;
1509
+		mb = (word >> 6) & 0x1f;
1510
+		me = (word >> 1) & 0x1f;
13911511 		rb = regs->gpr[rb] & 0x1f;
13921512 		val = DATA32(regs->gpr[rd]);
13931513 		op->val = ROTATE(val, rb) & MASK32(mb, me);
13941514 		goto logical_done;
13951515 
13961516 	case 24:	/* ori */
1397
-		op->val = regs->gpr[rd] | (unsigned short) instr;
1517
+		op->val = regs->gpr[rd] | (unsigned short) word;
13981518 		goto logical_done_nocc;
13991519 
14001520 	case 25:	/* oris */
1401
-		imm = (unsigned short) instr;
1521
+		imm = (unsigned short) word;
14021522 		op->val = regs->gpr[rd] | (imm << 16);
14031523 		goto logical_done_nocc;
14041524 
14051525 	case 26:	/* xori */
1406
-		op->val = regs->gpr[rd] ^ (unsigned short) instr;
1526
+		op->val = regs->gpr[rd] ^ (unsigned short) word;
14071527 		goto logical_done_nocc;
14081528 
14091529 	case 27:	/* xoris */
1410
-		imm = (unsigned short) instr;
1530
+		imm = (unsigned short) word;
14111531 		op->val = regs->gpr[rd] ^ (imm << 16);
14121532 		goto logical_done_nocc;
14131533 
14141534 	case 28:	/* andi. */
1415
-		op->val = regs->gpr[rd] & (unsigned short) instr;
1535
+		op->val = regs->gpr[rd] & (unsigned short) word;
14161536 		set_cr0(regs, op);
14171537 		goto logical_done_nocc;
14181538 
14191539 	case 29:	/* andis. */
1420
-		imm = (unsigned short) instr;
1540
+		imm = (unsigned short) word;
14211541 		op->val = regs->gpr[rd] & (imm << 16);
14221542 		set_cr0(regs, op);
14231543 		goto logical_done_nocc;
14241544 
14251545 #ifdef __powerpc64__
14261546 	case 30:	/* rld* */
1427
-		mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1547
+		mb = ((word >> 6) & 0x1f) | (word & 0x20);
14281548 		val = regs->gpr[rd];
1429
-		if ((instr & 0x10) == 0) {
1430
-			sh = rb | ((instr & 2) << 4);
1549
+		if ((word & 0x10) == 0) {
1550
+			sh = rb | ((word & 2) << 4);
14311551 			val = ROTATE(val, sh);
1432
-			switch ((instr >> 2) & 3) {
1552
+			switch ((word >> 2) & 3) {
14331553 			case 0:		/* rldicl */
14341554 				val &= MASK64_L(mb);
14351555 				break;
....@@ -1449,7 +1569,7 @@
14491569 		} else {
14501570 			sh = regs->gpr[rb] & 0x3f;
14511571 			val = ROTATE(val, sh);
1452
-			switch ((instr >> 1) & 7) {
1572
+			switch ((word >> 1) & 7) {
14531573 			case 0:		/* rldcl */
14541574 				op->val = val & MASK64_L(mb);
14551575 				goto logical_done;
....@@ -1464,8 +1584,8 @@
14641584 
14651585 	case 31:
14661586 		/* isel occupies 32 minor opcodes */
1467
-		if (((instr >> 1) & 0x1f) == 15) {
1468
-			mb = (instr >> 6) & 0x1f; /* bc field */
1587
+		if (((word >> 1) & 0x1f) == 15) {
1588
+			mb = (word >> 6) & 0x1f; /* bc field */
14691589 			val = (regs->ccr >> (31 - mb)) & 1;
14701590 			val2 = (ra) ? regs->gpr[ra] : 0;
14711591 
....@@ -1473,7 +1593,7 @@
14731593 			goto compute_done;
14741594 		}
14751595 
1476
-		switch ((instr >> 1) & 0x3ff) {
1596
+		switch ((word >> 1) & 0x3ff) {
14771597 		case 4:		/* tw */
14781598 			if (rd == 0x1f ||
14791599 			    (rd & trap_compare((int)regs->gpr[ra],
....@@ -1507,17 +1627,17 @@
15071627 			op->reg = rd;
15081628 			/* only MSR_EE and MSR_RI get changed if bit 15 set */
15091629 			/* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1510
-			imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1630
+			imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
15111631 			op->val = imm;
15121632 			return 0;
15131633 #endif
15141634 
15151635 		case 19:	/* mfcr */
15161636 			imm = 0xffffffffUL;
1517
-			if ((instr >> 20) & 1) {
1637
+			if ((word >> 20) & 1) {
15181638 				imm = 0xf0000000UL;
15191639 				for (sh = 0; sh < 8; ++sh) {
1520
-					if (instr & (0x80000 >> sh))
1640
+					if (word & (0x80000 >> sh))
15211641 						break;
15221642 					imm >>= 4;
15231643 				}
....@@ -1531,7 +1651,7 @@
15311651 			val = regs->gpr[rd];
15321652 			op->ccval = regs->ccr;
15331653 			for (sh = 0; sh < 8; ++sh) {
1534
-				if (instr & (0x80000 >> sh))
1654
+				if (word & (0x80000 >> sh))
15351655 					op->ccval = (op->ccval & ~imm) |
15361656 						(val & imm);
15371657 				imm >>= 4;
....@@ -1539,7 +1659,7 @@
15391659 			return 1;
15401660 
15411661 		case 339:	/* mfspr */
1542
-			spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1662
+			spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
15431663 			op->type = MFSPR;
15441664 			op->reg = rd;
15451665 			op->spr = spr;
....@@ -1549,7 +1669,7 @@
15491669 			return 0;
15501670 
15511671 		case 467:	/* mtspr */
1552
-			spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1672
+			spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
15531673 			op->type = MTSPR;
15541674 			op->val = regs->gpr[rd];
15551675 			op->spr = spr;
....@@ -1671,10 +1791,23 @@
16711791 				(int) regs->gpr[rb];
16721792 
16731793 			goto arith_done;
1674
-
1794
+#ifdef __powerpc64__
1795
+		case 265:	/* modud */
1796
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
1797
+				goto unknown_opcode;
1798
+			op->val = regs->gpr[ra] % regs->gpr[rb];
1799
+			goto compute_done;
1800
+#endif
16751801 		case 266:	/* add */
16761802 			op->val = regs->gpr[ra] + regs->gpr[rb];
16771803 			goto arith_done;
1804
+
1805
+		case 267:	/* moduw */
1806
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
1807
+				goto unknown_opcode;
1808
+			op->val = (unsigned int) regs->gpr[ra] %
1809
+				(unsigned int) regs->gpr[rb];
1810
+			goto compute_done;
16781811 #ifdef __powerpc64__
16791812 		case 457:	/* divdu */
16801813 			op->val = regs->gpr[ra] / regs->gpr[rb];
....@@ -1694,6 +1827,53 @@
16941827 			op->val = (int) regs->gpr[ra] /
16951828 				(int) regs->gpr[rb];
16961829 			goto arith_done;
1830
+#ifdef __powerpc64__
1831
+		case 425:	/* divde[.] */
1832
+			asm volatile(PPC_DIVDE(%0, %1, %2) :
1833
+				"=r" (op->val) : "r" (regs->gpr[ra]),
1834
+				"r" (regs->gpr[rb]));
1835
+			goto arith_done;
1836
+		case 393:	/* divdeu[.] */
1837
+			asm volatile(PPC_DIVDEU(%0, %1, %2) :
1838
+				"=r" (op->val) : "r" (regs->gpr[ra]),
1839
+				"r" (regs->gpr[rb]));
1840
+			goto arith_done;
1841
+#endif
1842
+		case 755:	/* darn */
1843
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
1844
+				goto unknown_opcode;
1845
+			switch (ra & 0x3) {
1846
+			case 0:
1847
+				/* 32-bit conditioned */
1848
+				asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1849
+				goto compute_done;
1850
+
1851
+			case 1:
1852
+				/* 64-bit conditioned */
1853
+				asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1854
+				goto compute_done;
1855
+
1856
+			case 2:
1857
+				/* 64-bit raw */
1858
+				asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1859
+				goto compute_done;
1860
+			}
1861
+
1862
+			goto unknown_opcode;
1863
+#ifdef __powerpc64__
1864
+		case 777:	/* modsd */
1865
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
1866
+				goto unknown_opcode;
1867
+			op->val = (long int) regs->gpr[ra] %
1868
+				(long int) regs->gpr[rb];
1869
+			goto compute_done;
1870
+#endif
1871
+		case 779:	/* modsw */
1872
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
1873
+				goto unknown_opcode;
1874
+			op->val = (int) regs->gpr[ra] %
1875
+				(int) regs->gpr[rb];
1876
+			goto compute_done;
16971877 
16981878 
16991879 /*
....@@ -1764,6 +1944,20 @@
17641944 		case 506:	/* popcntd */
17651945 			do_popcnt(regs, op, regs->gpr[rd], 64);
17661946 			goto logical_done_nocc;
1947
+#endif
1948
+		case 538:	/* cnttzw */
1949
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
1950
+				goto unknown_opcode;
1951
+			val = (unsigned int) regs->gpr[rd];
1952
+			op->val = (val ? __builtin_ctz(val) : 32);
1953
+			goto logical_done;
1954
+#ifdef __powerpc64__
1955
+		case 570:	/* cnttzd */
1956
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
1957
+				goto unknown_opcode;
1958
+			val = regs->gpr[rd];
1959
+			op->val = (val ? __builtin_ctzl(val) : 64);
1960
+			goto logical_done;
17671961 #endif
17681962 		case 922:	/* extsh */
17691963 			op->val = (signed short) regs->gpr[rd];
....@@ -1856,7 +2050,7 @@
18562050 		case 826:	/* sradi with sh_5 = 0 */
18572051 		case 827:	/* sradi with sh_5 = 1 */
18582052 			op->type = COMPUTE + SETREG + SETXER;
1859
-			sh = rb | ((instr & 2) << 4);
2053
+			sh = rb | ((word & 2) << 4);
18602054 			ival = (signed long int) regs->gpr[rd];
18612055 			op->val = ival >> sh;
18622056 			op->xerval = regs->xer;
....@@ -1866,6 +2060,20 @@
18662060 				op->xerval &= ~XER_CA;
18672061 			set_ca32(op, op->xerval & XER_CA);
18682062 			goto logical_done;
2063
+
2064
+		case 890:	/* extswsli with sh_5 = 0 */
2065
+		case 891:	/* extswsli with sh_5 = 1 */
2066
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2067
+				goto unknown_opcode;
2068
+			op->type = COMPUTE + SETREG;
2069
+			sh = rb | ((word & 2) << 4);
2070
+			val = (signed int) regs->gpr[rd];
2071
+			if (sh)
2072
+				op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2073
+			else
2074
+				op->val = val;
2075
+			goto logical_done;
2076
+
18692077 #endif /* __powerpc64__ */
18702078 
18712079 /*
....@@ -1873,34 +2081,34 @@
18732081  */
18742082 		case 54:	/* dcbst */
18752083 			op->type = MKOP(CACHEOP, DCBST, 0);
1876
-			op->ea = xform_ea(instr, regs);
2084
+			op->ea = xform_ea(word, regs);
18772085 			return 0;
18782086 
18792087 		case 86:	/* dcbf */
18802088 			op->type = MKOP(CACHEOP, DCBF, 0);
1881
-			op->ea = xform_ea(instr, regs);
2089
+			op->ea = xform_ea(word, regs);
18822090 			return 0;
18832091 
18842092 		case 246:	/* dcbtst */
18852093 			op->type = MKOP(CACHEOP, DCBTST, 0);
1886
-			op->ea = xform_ea(instr, regs);
2094
+			op->ea = xform_ea(word, regs);
18872095 			op->reg = rd;
18882096 			return 0;
18892097 
18902098 		case 278:	/* dcbt */
18912099 			op->type = MKOP(CACHEOP, DCBTST, 0);
1892
-			op->ea = xform_ea(instr, regs);
2100
+			op->ea = xform_ea(word, regs);
18932101 			op->reg = rd;
18942102 			return 0;
18952103 
18962104 		case 982:	/* icbi */
18972105 			op->type = MKOP(CACHEOP, ICBI, 0);
1898
-			op->ea = xform_ea(instr, regs);
2106
+			op->ea = xform_ea(word, regs);
18992107 			return 0;
19002108 
19012109 		case 1014:	/* dcbz */
19022110 			op->type = MKOP(CACHEOP, DCBZ, 0);
1903
-			op->ea = xform_ea(instr, regs);
2111
+			op->ea = xform_ea(word, regs);
19042112 			return 0;
19052113 		}
19062114 		break;
....@@ -1913,14 +2121,14 @@
19132121 	op->update_reg = ra;
19142122 	op->reg = rd;
19152123 	op->val = regs->gpr[rd];
1916
-	u = (instr >> 20) & UPDATE;
2124
+	u = (word >> 20) & UPDATE;
19172125 	op->vsx_flags = 0;
19182126 
19192127 	switch (opcode) {
19202128 	case 31:
1921
-		u = instr & UPDATE;
1922
-		op->ea = xform_ea(instr, regs);
1923
-		switch ((instr >> 1) & 0x3ff) {
2129
+		u = word & UPDATE;
2130
+		op->ea = xform_ea(word, regs);
2131
+		switch ((word >> 1) & 0x3ff) {
19242132 		case 20:	/* lwarx */
19252133 			op->type = MKOP(LARX, 0, 4);
19262134 			break;
....@@ -2165,25 +2373,27 @@
21652373 
21662374 #ifdef CONFIG_VSX
21672375 		case 12:	/* lxsiwzx */
2168
-			op->reg = rd | ((instr & 1) << 5);
2376
+			op->reg = rd | ((word & 1) << 5);
21692377 			op->type = MKOP(LOAD_VSX, 0, 4);
21702378 			op->element_size = 8;
21712379 			break;
21722380 
21732381 		case 76:	/* lxsiwax */
2174
-			op->reg = rd | ((instr & 1) << 5);
2382
+			op->reg = rd | ((word & 1) << 5);
21752383 			op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
21762384 			op->element_size = 8;
21772385 			break;
21782386 
21792387 		case 140:	/* stxsiwx */
2180
-			op->reg = rd | ((instr & 1) << 5);
2388
+			op->reg = rd | ((word & 1) << 5);
21812389 			op->type = MKOP(STORE_VSX, 0, 4);
21822390 			op->element_size = 8;
21832391 			break;
21842392 
21852393 		case 268:	/* lxvx */
2186
-			op->reg = rd | ((instr & 1) << 5);
2394
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2395
+				goto unknown_opcode;
2396
+			op->reg = rd | ((word & 1) << 5);
21872397 			op->type = MKOP(LOAD_VSX, 0, 16);
21882398 			op->element_size = 16;
21892399 			op->vsx_flags = VSX_CHECK_VEC;
....@@ -2192,33 +2402,39 @@
21922402 		case 269:	/* lxvl */
21932403 		case 301: {	/* lxvll */
21942404 			int nb;
2195
-			op->reg = rd | ((instr & 1) << 5);
2405
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2406
+				goto unknown_opcode;
2407
+			op->reg = rd | ((word & 1) << 5);
21962408 			op->ea = ra ? regs->gpr[ra] : 0;
21972409 			nb = regs->gpr[rb] & 0xff;
21982410 			if (nb > 16)
21992411 				nb = 16;
22002412 			op->type = MKOP(LOAD_VSX, 0, nb);
22012413 			op->element_size = 16;
2202
-			op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2414
+			op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
22032415 				VSX_CHECK_VEC;
22042416 			break;
22052417 		}
22062418 		case 332:	/* lxvdsx */
2207
-			op->reg = rd | ((instr & 1) << 5);
2419
+			op->reg = rd | ((word & 1) << 5);
22082420 			op->type = MKOP(LOAD_VSX, 0, 8);
22092421 			op->element_size = 8;
22102422 			op->vsx_flags = VSX_SPLAT;
22112423 			break;
22122424 
22132425 		case 364:	/* lxvwsx */
2214
-			op->reg = rd | ((instr & 1) << 5);
2426
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2427
+				goto unknown_opcode;
2428
+			op->reg = rd | ((word & 1) << 5);
22152429 			op->type = MKOP(LOAD_VSX, 0, 4);
22162430 			op->element_size = 4;
22172431 			op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
22182432 			break;
22192433 
22202434 		case 396:	/* stxvx */
2221
-			op->reg = rd | ((instr & 1) << 5);
2435
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2436
+				goto unknown_opcode;
2437
+			op->reg = rd | ((word & 1) << 5);
22222438 			op->type = MKOP(STORE_VSX, 0, 16);
22232439 			op->element_size = 16;
22242440 			op->vsx_flags = VSX_CHECK_VEC;
....@@ -2227,118 +2443,136 @@
22272443 		case 397:	/* stxvl */
22282444 		case 429: {	/* stxvll */
22292445 			int nb;
2230
-			op->reg = rd | ((instr & 1) << 5);
2446
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2447
+				goto unknown_opcode;
2448
+			op->reg = rd | ((word & 1) << 5);
22312449 			op->ea = ra ? regs->gpr[ra] : 0;
22322450 			nb = regs->gpr[rb] & 0xff;
22332451 			if (nb > 16)
22342452 				nb = 16;
22352453 			op->type = MKOP(STORE_VSX, 0, nb);
22362454 			op->element_size = 16;
2237
-			op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2455
+			op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
22382456 				VSX_CHECK_VEC;
22392457 			break;
22402458 		}
22412459 		case 524:	/* lxsspx */
2242
-			op->reg = rd | ((instr & 1) << 5);
2460
+			op->reg = rd | ((word & 1) << 5);
22432461 			op->type = MKOP(LOAD_VSX, 0, 4);
22442462 			op->element_size = 8;
22452463 			op->vsx_flags = VSX_FPCONV;
22462464 			break;
22472465 
22482466 		case 588:	/* lxsdx */
2249
-			op->reg = rd | ((instr & 1) << 5);
2467
+			op->reg = rd | ((word & 1) << 5);
22502468 			op->type = MKOP(LOAD_VSX, 0, 8);
22512469 			op->element_size = 8;
22522470 			break;
22532471 
22542472 		case 652:	/* stxsspx */
2255
-			op->reg = rd | ((instr & 1) << 5);
2473
+			op->reg = rd | ((word & 1) << 5);
22562474 			op->type = MKOP(STORE_VSX, 0, 4);
22572475 			op->element_size = 8;
22582476 			op->vsx_flags = VSX_FPCONV;
22592477 			break;
22602478 
22612479 		case 716:	/* stxsdx */
2262
-			op->reg = rd | ((instr & 1) << 5);
2480
+			op->reg = rd | ((word & 1) << 5);
22632481 			op->type = MKOP(STORE_VSX, 0, 8);
22642482 			op->element_size = 8;
22652483 			break;
22662484 
22672485 		case 780:	/* lxvw4x */
2268
-			op->reg = rd | ((instr & 1) << 5);
2486
+			op->reg = rd | ((word & 1) << 5);
22692487 			op->type = MKOP(LOAD_VSX, 0, 16);
22702488 			op->element_size = 4;
22712489 			break;
22722490 
22732491 		case 781:	/* lxsibzx */
2274
-			op->reg = rd | ((instr & 1) << 5);
2492
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2493
+				goto unknown_opcode;
2494
+			op->reg = rd | ((word & 1) << 5);
22752495 			op->type = MKOP(LOAD_VSX, 0, 1);
22762496 			op->element_size = 8;
22772497 			op->vsx_flags = VSX_CHECK_VEC;
22782498 			break;
22792499 
22802500 		case 812:	/* lxvh8x */
2281
-			op->reg = rd | ((instr & 1) << 5);
2501
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2502
+				goto unknown_opcode;
2503
+			op->reg = rd | ((word & 1) << 5);
22822504 			op->type = MKOP(LOAD_VSX, 0, 16);
22832505 			op->element_size = 2;
22842506 			op->vsx_flags = VSX_CHECK_VEC;
22852507 			break;
22862508 
22872509 		case 813:	/* lxsihzx */
2288
-			op->reg = rd | ((instr & 1) << 5);
2510
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2511
+				goto unknown_opcode;
2512
+			op->reg = rd | ((word & 1) << 5);
22892513 			op->type = MKOP(LOAD_VSX, 0, 2);
22902514 			op->element_size = 8;
22912515 			op->vsx_flags = VSX_CHECK_VEC;
22922516 			break;
22932517 
22942518 		case 844:	/* lxvd2x */
2295
-			op->reg = rd | ((instr & 1) << 5);
2519
+			op->reg = rd | ((word & 1) << 5);
22962520 			op->type = MKOP(LOAD_VSX, 0, 16);
22972521 			op->element_size = 8;
22982522 			break;
22992523 
23002524 		case 876:	/* lxvb16x */
2301
-			op->reg = rd | ((instr & 1) << 5);
2525
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2526
+				goto unknown_opcode;
2527
+			op->reg = rd | ((word & 1) << 5);
23022528 			op->type = MKOP(LOAD_VSX, 0, 16);
23032529 			op->element_size = 1;
23042530 			op->vsx_flags = VSX_CHECK_VEC;
23052531 			break;
23062532 
23072533 		case 908:	/* stxvw4x */
2308
-			op->reg = rd | ((instr & 1) << 5);
2534
+			op->reg = rd | ((word & 1) << 5);
23092535 			op->type = MKOP(STORE_VSX, 0, 16);
23102536 			op->element_size = 4;
23112537 			break;
23122538 
23132539 		case 909:	/* stxsibx */
2314
-			op->reg = rd | ((instr & 1) << 5);
2540
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2541
+				goto unknown_opcode;
2542
+			op->reg = rd | ((word & 1) << 5);
23152543 			op->type = MKOP(STORE_VSX, 0, 1);
23162544 			op->element_size = 8;
23172545 			op->vsx_flags = VSX_CHECK_VEC;
23182546 			break;
23192547 
23202548 		case 940:	/* stxvh8x */
2321
-			op->reg = rd | ((instr & 1) << 5);
2549
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2550
+				goto unknown_opcode;
2551
+			op->reg = rd | ((word & 1) << 5);
23222552 			op->type = MKOP(STORE_VSX, 0, 16);
23232553 			op->element_size = 2;
23242554 			op->vsx_flags = VSX_CHECK_VEC;
23252555 			break;
23262556 
23272557 		case 941:	/* stxsihx */
2328
-			op->reg = rd | ((instr & 1) << 5);
2558
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2559
+				goto unknown_opcode;
2560
+			op->reg = rd | ((word & 1) << 5);
23292561 			op->type = MKOP(STORE_VSX, 0, 2);
23302562 			op->element_size = 8;
23312563 			op->vsx_flags = VSX_CHECK_VEC;
23322564 			break;
23332565 
23342566 		case 972:	/* stxvd2x */
2335
-			op->reg = rd | ((instr & 1) << 5);
2567
+			op->reg = rd | ((word & 1) << 5);
23362568 			op->type = MKOP(STORE_VSX, 0, 16);
23372569 			op->element_size = 8;
23382570 			break;
23392571 
23402572 		case 1004:	/* stxvb16x */
2341
-			op->reg = rd | ((instr & 1) << 5);
2573
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2574
+				goto unknown_opcode;
2575
+			op->reg = rd | ((word & 1) << 5);
23422576 			op->type = MKOP(STORE_VSX, 0, 16);
23432577 			op->element_size = 1;
23442578 			op->vsx_flags = VSX_CHECK_VEC;
....@@ -2351,80 +2585,80 @@
23512585 	case 32:	/* lwz */
23522586 	case 33:	/* lwzu */
23532587 		op->type = MKOP(LOAD, u, 4);
2354
-		op->ea = dform_ea(instr, regs);
2588
+		op->ea = dform_ea(word, regs);
23552589 		break;
23562590 
23572591 	case 34:	/* lbz */
23582592 	case 35:	/* lbzu */
23592593 		op->type = MKOP(LOAD, u, 1);
2360
-		op->ea = dform_ea(instr, regs);
2594
+		op->ea = dform_ea(word, regs);
23612595 		break;
23622596 
23632597 	case 36:	/* stw */
23642598 	case 37:	/* stwu */
23652599 		op->type = MKOP(STORE, u, 4);
2366
-		op->ea = dform_ea(instr, regs);
2600
+		op->ea = dform_ea(word, regs);
23672601 		break;
23682602 
23692603 	case 38:	/* stb */
23702604 	case 39:	/* stbu */
23712605 		op->type = MKOP(STORE, u, 1);
2372
-		op->ea = dform_ea(instr, regs);
2606
+		op->ea = dform_ea(word, regs);
23732607 		break;
23742608 
23752609 	case 40:	/* lhz */
23762610 	case 41:	/* lhzu */
23772611 		op->type = MKOP(LOAD, u, 2);
2378
-		op->ea = dform_ea(instr, regs);
2612
+		op->ea = dform_ea(word, regs);
23792613 		break;
23802614 
23812615 	case 42:	/* lha */
23822616 	case 43:	/* lhau */
23832617 		op->type = MKOP(LOAD, SIGNEXT | u, 2);
2384
-		op->ea = dform_ea(instr, regs);
2618
+		op->ea = dform_ea(word, regs);
23852619 		break;
23862620 
23872621 	case 44:	/* sth */
23882622 	case 45:	/* sthu */
23892623 		op->type = MKOP(STORE, u, 2);
2390
-		op->ea = dform_ea(instr, regs);
2624
+		op->ea = dform_ea(word, regs);
23912625 		break;
23922626 
23932627 	case 46:	/* lmw */
23942628 		if (ra >= rd)
23952629 			break;		/* invalid form, ra in range to load */
23962630 		op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2397
-		op->ea = dform_ea(instr, regs);
2631
+		op->ea = dform_ea(word, regs);
23982632 		break;
23992633 
24002634 	case 47:	/* stmw */
24012635 		op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2402
-		op->ea = dform_ea(instr, regs);
2636
+		op->ea = dform_ea(word, regs);
24032637 		break;
24042638 
24052639 #ifdef CONFIG_PPC_FPU
24062640 	case 48:	/* lfs */
24072641 	case 49:	/* lfsu */
24082642 		op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2409
-		op->ea = dform_ea(instr, regs);
2643
+		op->ea = dform_ea(word, regs);
24102644 		break;
24112645 
24122646 	case 50:	/* lfd */
24132647 	case 51:	/* lfdu */
24142648 		op->type = MKOP(LOAD_FP, u, 8);
2415
-		op->ea = dform_ea(instr, regs);
2649
+		op->ea = dform_ea(word, regs);
24162650 		break;
24172651 
24182652 	case 52:	/* stfs */
24192653 	case 53:	/* stfsu */
24202654 		op->type = MKOP(STORE_FP, u | FPCONV, 4);
2421
-		op->ea = dform_ea(instr, regs);
2655
+		op->ea = dform_ea(word, regs);
24222656 		break;
24232657 
24242658 	case 54:	/* stfd */
24252659 	case 55:	/* stfdu */
24262660 		op->type = MKOP(STORE_FP, u, 8);
2427
-		op->ea = dform_ea(instr, regs);
2661
+		op->ea = dform_ea(word, regs);
24282662 		break;
24292663 #endif
24302664 
....@@ -2432,26 +2666,30 @@
24322666 	case 56:	/* lq */
24332667 		if (!((rd & 1) || (rd == ra)))
24342668 			op->type = MKOP(LOAD, 0, 16);
2435
-		op->ea = dqform_ea(instr, regs);
2669
+		op->ea = dqform_ea(word, regs);
24362670 		break;
24372671 #endif
24382672 
24392673 #ifdef CONFIG_VSX
24402674 	case 57:	/* lfdp, lxsd, lxssp */
2441
-		op->ea = dsform_ea(instr, regs);
2442
-		switch (instr & 3) {
2675
+		op->ea = dsform_ea(word, regs);
2676
+		switch (word & 3) {
24432677 		case 0:		/* lfdp */
24442678 			if (rd & 1)
24452679 				break;		/* reg must be even */
24462680 			op->type = MKOP(LOAD_FP, 0, 16);
24472681 			break;
24482682 		case 2:		/* lxsd */
2683
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2684
+				goto unknown_opcode;
24492685 			op->reg = rd + 32;
24502686 			op->type = MKOP(LOAD_VSX, 0, 8);
24512687 			op->element_size = 8;
24522688 			op->vsx_flags = VSX_CHECK_VEC;
24532689 			break;
24542690 		case 3:		/* lxssp */
2691
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2692
+				goto unknown_opcode;
24552693 			op->reg = rd + 32;
24562694 			op->type = MKOP(LOAD_VSX, 0, 4);
24572695 			op->element_size = 8;
....@@ -2463,8 +2701,8 @@
24632701 
24642702 #ifdef __powerpc64__
24652703 	case 58:	/* ld[u], lwa */
2466
-		op->ea = dsform_ea(instr, regs);
2467
-		switch (instr & 3) {
2704
+		op->ea = dsform_ea(word, regs);
2705
+		switch (word & 3) {
24682706 		case 0:		/* ld */
24692707 			op->type = MKOP(LOAD, 0, 8);
24702708 			break;
....@@ -2480,16 +2718,18 @@
24802718 
24812719 #ifdef CONFIG_VSX
24822720 	case 61:	/* stfdp, lxv, stxsd, stxssp, stxv */
2483
-		switch (instr & 7) {
2721
+		switch (word & 7) {
24842722 		case 0:		/* stfdp with LSB of DS field = 0 */
24852723 		case 4:		/* stfdp with LSB of DS field = 1 */
2486
-			op->ea = dsform_ea(instr, regs);
2724
+			op->ea = dsform_ea(word, regs);
24872725 			op->type = MKOP(STORE_FP, 0, 16);
24882726 			break;
24892727 
24902728 		case 1:		/* lxv */
2491
-			op->ea = dqform_ea(instr, regs);
2492
-			if (instr & 8)
2729
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2730
+				goto unknown_opcode;
2731
+			op->ea = dqform_ea(word, regs);
2732
+			if (word & 8)
24932733 				op->reg = rd + 32;
24942734 			op->type = MKOP(LOAD_VSX, 0, 16);
24952735 			op->element_size = 16;
....@@ -2498,7 +2738,9 @@
24982738 
24992739 		case 2:		/* stxsd with LSB of DS field = 0 */
25002740 		case 6:		/* stxsd with LSB of DS field = 1 */
2501
-			op->ea = dsform_ea(instr, regs);
2741
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2742
+				goto unknown_opcode;
2743
+			op->ea = dsform_ea(word, regs);
25022744 			op->reg = rd + 32;
25032745 			op->type = MKOP(STORE_VSX, 0, 8);
25042746 			op->element_size = 8;
....@@ -2507,7 +2749,9 @@
25072749 
25082750 		case 3:		/* stxssp with LSB of DS field = 0 */
25092751 		case 7:		/* stxssp with LSB of DS field = 1 */
2510
-			op->ea = dsform_ea(instr, regs);
2752
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2753
+				goto unknown_opcode;
2754
+			op->ea = dsform_ea(word, regs);
25112755 			op->reg = rd + 32;
25122756 			op->type = MKOP(STORE_VSX, 0, 4);
25132757 			op->element_size = 8;
....@@ -2515,8 +2759,10 @@
25152759 			break;
25162760 
25172761 		case 5:		/* stxv */
2518
-			op->ea = dqform_ea(instr, regs);
2519
-			if (instr & 8)
2762
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
2763
+				goto unknown_opcode;
2764
+			op->ea = dqform_ea(word, regs);
2765
+			if (word & 8)
25202766 				op->reg = rd + 32;
25212767 			op->type = MKOP(STORE_VSX, 0, 16);
25222768 			op->element_size = 16;
....@@ -2528,8 +2774,8 @@
25282774 
25292775 #ifdef __powerpc64__
25302776 	case 62:	/* std[u] */
2531
-		op->ea = dsform_ea(instr, regs);
2532
-		switch (instr & 3) {
2777
+		op->ea = dsform_ea(word, regs);
2778
+		switch (word & 3) {
25332779 		case 0:		/* std */
25342780 			op->type = MKOP(STORE, 0, 8);
25352781 			break;
....@@ -2542,8 +2788,145 @@
25422788 			break;
25432789 		}
25442790 		break;
2791
+	case 1: /* Prefixed instructions */
2792
+		if (!cpu_has_feature(CPU_FTR_ARCH_31))
2793
+			goto unknown_opcode;
2794
+
2795
+		prefix_r = GET_PREFIX_R(word);
2796
+		ra = GET_PREFIX_RA(suffix);
2797
+		op->update_reg = ra;
2798
+		rd = (suffix >> 21) & 0x1f;
2799
+		op->reg = rd;
2800
+		op->val = regs->gpr[rd];
2801
+
2802
+		suffixopcode = get_op(suffix);
2803
+		prefixtype = (word >> 24) & 0x3;
2804
+		switch (prefixtype) {
2805
+		case 0: /* Type 00  Eight-Byte Load/Store */
2806
+			if (prefix_r && ra)
2807
+				break;
2808
+			op->ea = mlsd_8lsd_ea(word, suffix, regs);
2809
+			switch (suffixopcode) {
2810
+			case 41:	/* plwa */
2811
+				op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2812
+				break;
2813
+#ifdef CONFIG_VSX
2814
+			case 42:        /* plxsd */
2815
+				op->reg = rd + 32;
2816
+				op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2817
+				op->element_size = 8;
2818
+				op->vsx_flags = VSX_CHECK_VEC;
2819
+				break;
2820
+			case 43:	/* plxssp */
2821
+				op->reg = rd + 32;
2822
+				op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2823
+				op->element_size = 8;
2824
+				op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2825
+				break;
2826
+			case 46:	/* pstxsd */
2827
+				op->reg = rd + 32;
2828
+				op->type = MKOP(STORE_VSX, PREFIXED, 8);
2829
+				op->element_size = 8;
2830
+				op->vsx_flags = VSX_CHECK_VEC;
2831
+				break;
2832
+			case 47:	/* pstxssp */
2833
+				op->reg = rd + 32;
2834
+				op->type = MKOP(STORE_VSX, PREFIXED, 4);
2835
+				op->element_size = 8;
2836
+				op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2837
+				break;
2838
+			case 51:	/* plxv1 */
2839
+				op->reg += 32;
2840
+				fallthrough;
2841
+			case 50:	/* plxv0 */
2842
+				op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2843
+				op->element_size = 16;
2844
+				op->vsx_flags = VSX_CHECK_VEC;
2845
+				break;
2846
+			case 55:	/* pstxv1 */
2847
+				op->reg = rd + 32;
2848
+				fallthrough;
2849
+			case 54:	/* pstxv0 */
2850
+				op->type = MKOP(STORE_VSX, PREFIXED, 16);
2851
+				op->element_size = 16;
2852
+				op->vsx_flags = VSX_CHECK_VEC;
2853
+				break;
2854
+#endif /* CONFIG_VSX */
2855
+			case 56:        /* plq */
2856
+				op->type = MKOP(LOAD, PREFIXED, 16);
2857
+				break;
2858
+			case 57:	/* pld */
2859
+				op->type = MKOP(LOAD, PREFIXED, 8);
2860
+				break;
2861
+			case 60:        /* pstq */
2862
+				op->type = MKOP(STORE, PREFIXED, 16);
2863
+				break;
2864
+			case 61:	/* pstd */
2865
+				op->type = MKOP(STORE, PREFIXED, 8);
2866
+				break;
2867
+			}
2868
+			break;
2869
+		case 1: /* Type 01 Eight-Byte Register-to-Register */
2870
+			break;
2871
+		case 2: /* Type 10 Modified Load/Store */
2872
+			if (prefix_r && ra)
2873
+				break;
2874
+			op->ea = mlsd_8lsd_ea(word, suffix, regs);
2875
+			switch (suffixopcode) {
2876
+			case 32:	/* plwz */
2877
+				op->type = MKOP(LOAD, PREFIXED, 4);
2878
+				break;
2879
+			case 34:	/* plbz */
2880
+				op->type = MKOP(LOAD, PREFIXED, 1);
2881
+				break;
2882
+			case 36:	/* pstw */
2883
+				op->type = MKOP(STORE, PREFIXED, 4);
2884
+				break;
2885
+			case 38:	/* pstb */
2886
+				op->type = MKOP(STORE, PREFIXED, 1);
2887
+				break;
2888
+			case 40:	/* plhz */
2889
+				op->type = MKOP(LOAD, PREFIXED, 2);
2890
+				break;
2891
+			case 42:	/* plha */
2892
+				op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
2893
+				break;
2894
+			case 44:	/* psth */
2895
+				op->type = MKOP(STORE, PREFIXED, 2);
2896
+				break;
2897
+			case 48:        /* plfs */
2898
+				op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
2899
+				break;
2900
+			case 50:        /* plfd */
2901
+				op->type = MKOP(LOAD_FP, PREFIXED, 8);
2902
+				break;
2903
+			case 52:        /* pstfs */
2904
+				op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
2905
+				break;
2906
+			case 54:        /* pstfd */
2907
+				op->type = MKOP(STORE_FP, PREFIXED, 8);
2908
+				break;
2909
+			}
2910
+			break;
2911
+		case 3: /* Type 11 Modified Register-to-Register */
2912
+			break;
2913
+		}
25452914 #endif /* __powerpc64__ */
25462915 
2916
+	}
2917
+
2918
+	if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {
2919
+		switch (GETTYPE(op->type)) {
2920
+		case LOAD:
2921
+			if (ra == rd)
2922
+				goto unknown_opcode;
2923
+			fallthrough;
2924
+		case STORE:
2925
+		case LOAD_FP:
2926
+		case STORE_FP:
2927
+			if (ra == 0)
2928
+				goto unknown_opcode;
2929
+		}
25472930 	}
25482931 
25492932 #ifdef CONFIG_VSX
....@@ -2556,8 +2939,12 @@
25562939 
25572940 	return 0;
25582941 
2942
+ unknown_opcode:
2943
+	op->type = UNKNOWN;
2944
+	return 0;
2945
+
25592946  logical_done:
2560
-	if (instr & 1)
2947
+	if (word & 1)
25612948 		set_cr0(regs, op);
25622949  logical_done_nocc:
25632950 	op->reg = ra;
....@@ -2565,7 +2952,7 @@
25652952 	return 1;
25662953 
25672954  arith_done:
2568
-	if (instr & 1)
2955
+	if (word & 1)
25692956 		set_cr0(regs, op);
25702957  compute_done:
25712958 	op->reg = rd;
....@@ -2650,7 +3037,7 @@
26503037 {
26513038 	unsigned long next_pc;
26523039 
2653
-	next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
3040
+	next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
26543041 	switch (GETTYPE(op->type)) {
26553042 	case COMPUTE:
26563043 		if (op->type & SETREG)
....@@ -2806,7 +3193,7 @@
28063193 			__put_user_asmx(op->val, ea, err, "stbcx.", cr);
28073194 			break;
28083195 		case 2:
2809
-			__put_user_asmx(op->val, ea, err, "stbcx.", cr);
3196
+			__put_user_asmx(op->val, ea, err, "sthcx.", cr);
28103197 			break;
28113198 #endif
28123199 		case 4:
....@@ -2997,7 +3384,7 @@
29973384  * or -1 if the instruction is one that should not be stepped,
29983385  * such as an rfid, or a mtmsrd that would clear MSR_RI.
29993386  */
3000
-int emulate_step(struct pt_regs *regs, unsigned int instr)
3387
+int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
30013388 {
30023389 	struct instruction_op op;
30033390 	int r, err, type;
....@@ -3075,8 +3462,9 @@
30753462 		 * entry code works.  If that is changed, this will
30763463 		 * need to be changed also.
30773464 		 */
3078
-		if (regs->gpr[0] == 0x1ebe &&
3079
-		    cpu_has_feature(CPU_FTR_REAL_LE)) {
3465
+		if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3466
+				cpu_has_feature(CPU_FTR_REAL_LE) &&
3467
+				regs->gpr[0] == 0x1ebe) {
30803468 			regs->msr ^= MSR_LE;
30813469 			goto instr_done;
30823470 		}
....@@ -3089,6 +3477,18 @@
30893477 		regs->msr = MSR_KERNEL;
30903478 		return 1;
30913479 
3480
+#ifdef CONFIG_PPC_BOOK3S_64
3481
+	case SYSCALL_VECTORED_0:	/* scv 0 */
3482
+		regs->gpr[9] = regs->gpr[13];
3483
+		regs->gpr[10] = MSR_KERNEL;
3484
+		regs->gpr[11] = regs->nip + 4;
3485
+		regs->gpr[12] = regs->msr & MSR_MASK;
3486
+		regs->gpr[13] = (unsigned long) get_paca();
3487
+		regs->nip = (unsigned long) &system_call_vectored_emulate;
3488
+		regs->msr = MSR_KERNEL;
3489
+		return 1;
3490
+#endif
3491
+
30923492 	case RFI:
30933493 		return -1;
30943494 #endif
....@@ -3096,7 +3496,7 @@
30963496 	return 0;
30973497 
30983498  instr_done:
3099
-	regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
3499
+	regs->nip = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type));
31003500 	return 1;
31013501 }
31023502 NOKPROBE_SYMBOL(emulate_step);