.. | .. |
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| 1 | +/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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1 | 2 | /* |
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2 | 3 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> |
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3 | 4 | * Initial PowerPC version. |
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.. | .. |
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18 | 19 | * frank_rowand@mvista.com or source@mvista.com |
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19 | 20 | * debbie_chu@mvista.com |
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20 | 21 | * |
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21 | | - * |
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22 | 22 | * Module name: head_4xx.S |
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23 | 23 | * |
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24 | 24 | * Description: |
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25 | 25 | * Kernel execution entry point code. |
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26 | | - * |
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27 | | - * This program is free software; you can redistribute it and/or |
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28 | | - * modify it under the terms of the GNU General Public License |
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29 | | - * as published by the Free Software Foundation; either version |
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30 | | - * 2 of the License, or (at your option) any later version. |
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31 | | - * |
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32 | 26 | */ |
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33 | 27 | |
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34 | 28 | #include <linux/init.h> |
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| 29 | +#include <linux/pgtable.h> |
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| 30 | +#include <linux/sizes.h> |
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35 | 31 | #include <asm/processor.h> |
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36 | 32 | #include <asm/page.h> |
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37 | 33 | #include <asm/mmu.h> |
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38 | | -#include <asm/pgtable.h> |
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39 | 34 | #include <asm/cputable.h> |
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40 | 35 | #include <asm/thread_info.h> |
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41 | 36 | #include <asm/ppc_asm.h> |
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42 | 37 | #include <asm/asm-offsets.h> |
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43 | 38 | #include <asm/ptrace.h> |
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44 | 39 | #include <asm/export.h> |
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45 | | -#include <asm/asm-405.h> |
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| 40 | + |
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| 41 | +#include "head_32.h" |
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46 | 42 | |
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47 | 43 | /* As with the other PowerPC ports, it is expected that when code |
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48 | 44 | * execution begins here, the following registers contain valid, yet |
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.. | .. |
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77 | 73 | lis r0,start_here@h |
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78 | 74 | ori r0,r0,start_here@l |
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79 | 75 | mtspr SPRN_SRR0,r0 |
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80 | | - SYNC |
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81 | 76 | rfi /* enables MMU */ |
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82 | 77 | b . /* prevent prefetch past rfi */ |
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83 | 78 | |
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.. | .. |
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99 | 94 | .space 4 |
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100 | 95 | |
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101 | 96 | /* |
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102 | | - * Exception vector entry code. This code runs with address translation |
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103 | | - * turned off (i.e. using physical addresses). We assume SPRG_THREAD has |
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104 | | - * the physical address of the current task thread_struct. |
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105 | | - * Note that we have to have decremented r1 before we write to any fields |
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106 | | - * of the exception frame, since a critical interrupt could occur at any |
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107 | | - * time, and it will write to the area immediately below the current r1. |
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108 | | - */ |
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109 | | -#define NORMAL_EXCEPTION_PROLOG \ |
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110 | | - mtspr SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\ |
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111 | | - mtspr SPRN_SPRG_SCRATCH1,r11; \ |
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112 | | - mtspr SPRN_SPRG_SCRATCH2,r1; \ |
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113 | | - mfcr r10; /* save CR in r10 for now */\ |
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114 | | - mfspr r11,SPRN_SRR1; /* check whether user or kernel */\ |
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115 | | - andi. r11,r11,MSR_PR; \ |
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116 | | - beq 1f; \ |
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117 | | - mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\ |
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118 | | - lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\ |
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119 | | - addi r1,r1,THREAD_SIZE; \ |
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120 | | -1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\ |
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121 | | - tophys(r11,r1); \ |
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122 | | - stw r10,_CCR(r11); /* save various registers */\ |
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123 | | - stw r12,GPR12(r11); \ |
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124 | | - stw r9,GPR9(r11); \ |
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125 | | - mfspr r10,SPRN_SPRG_SCRATCH0; \ |
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126 | | - stw r10,GPR10(r11); \ |
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127 | | - mfspr r12,SPRN_SPRG_SCRATCH1; \ |
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128 | | - stw r12,GPR11(r11); \ |
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129 | | - mflr r10; \ |
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130 | | - stw r10,_LINK(r11); \ |
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131 | | - mfspr r10,SPRN_SPRG_SCRATCH2; \ |
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132 | | - mfspr r12,SPRN_SRR0; \ |
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133 | | - stw r10,GPR1(r11); \ |
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134 | | - mfspr r9,SPRN_SRR1; \ |
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135 | | - stw r10,0(r11); \ |
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136 | | - rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ |
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137 | | - stw r0,GPR0(r11); \ |
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138 | | - SAVE_4GPRS(3, r11); \ |
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139 | | - SAVE_2GPRS(7, r11) |
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140 | | - |
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141 | | -/* |
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142 | 97 | * Exception prolog for critical exceptions. This is a little different |
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143 | 98 | * from the normal exception prolog above since a critical exception |
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144 | 99 | * can potentially occur at any point during normal exception processing. |
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.. | .. |
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158 | 113 | beq 1f; \ |
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159 | 114 | /* COMING FROM USER MODE */ \ |
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160 | 115 | mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ |
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161 | | - lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ |
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| 116 | + lwz r11,TASK_STACK-THREAD(r11); /* this thread's kernel stack */\ |
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162 | 117 | 1: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\ |
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163 | 118 | tophys(r11,r11); \ |
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164 | 119 | stw r10,_CCR(r11); /* save various registers */\ |
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.. | .. |
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177 | 132 | tovirt(r1,r11); \ |
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178 | 133 | rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ |
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179 | 134 | stw r0,GPR0(r11); \ |
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| 135 | + lis r10, STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */\ |
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| 136 | + addi r10, r10, STACK_FRAME_REGS_MARKER@l; \ |
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| 137 | + stw r10, 8(r11); \ |
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180 | 138 | SAVE_4GPRS(3, r11); \ |
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181 | 139 | SAVE_2GPRS(7, r11) |
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182 | 140 | |
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.. | .. |
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196 | 154 | /* |
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197 | 155 | * Exception vectors. |
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198 | 156 | */ |
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199 | | -#define START_EXCEPTION(n, label) \ |
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200 | | - . = n; \ |
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201 | | -label: |
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202 | | - |
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203 | | -#define EXCEPTION(n, label, hdlr, xfer) \ |
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204 | | - START_EXCEPTION(n, label); \ |
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205 | | - NORMAL_EXCEPTION_PROLOG; \ |
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206 | | - addi r3,r1,STACK_FRAME_OVERHEAD; \ |
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207 | | - xfer(n, hdlr) |
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208 | | - |
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209 | 157 | #define CRITICAL_EXCEPTION(n, label, hdlr) \ |
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210 | 158 | START_EXCEPTION(n, label); \ |
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211 | 159 | CRITICAL_EXCEPTION_PROLOG; \ |
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212 | 160 | addi r3,r1,STACK_FRAME_OVERHEAD; \ |
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213 | 161 | EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ |
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214 | | - NOCOPY, crit_transfer_to_handler, \ |
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215 | | - ret_from_crit_exc) |
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216 | | - |
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217 | | -#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ |
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218 | | - li r10,trap; \ |
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219 | | - stw r10,_TRAP(r11); \ |
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220 | | - lis r10,msr@h; \ |
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221 | | - ori r10,r10,msr@l; \ |
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222 | | - copyee(r10, r9); \ |
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223 | | - bl tfer; \ |
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224 | | - .long hdlr; \ |
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225 | | - .long ret |
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226 | | - |
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227 | | -#define COPY_EE(d, s) rlwimi d,s,0,16,16 |
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228 | | -#define NOCOPY(d, s) |
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229 | | - |
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230 | | -#define EXC_XFER_STD(n, hdlr) \ |
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231 | | - EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ |
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232 | | - ret_from_except_full) |
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233 | | - |
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234 | | -#define EXC_XFER_LITE(n, hdlr) \ |
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235 | | - EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ |
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236 | | - ret_from_except) |
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237 | | - |
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238 | | -#define EXC_XFER_EE(n, hdlr) \ |
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239 | | - EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ |
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240 | | - ret_from_except_full) |
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241 | | - |
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242 | | -#define EXC_XFER_EE_LITE(n, hdlr) \ |
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243 | | - EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ |
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244 | | - ret_from_except) |
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245 | | - |
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| 162 | + crit_transfer_to_handler, ret_from_crit_exc) |
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246 | 163 | |
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247 | 164 | /* |
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248 | 165 | * 0x0100 - Critical Interrupt Exception |
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.. | .. |
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258 | 175 | * 0x0300 - Data Storage Exception |
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259 | 176 | * This happens for just a few reasons. U0 set (but we don't do that), |
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260 | 177 | * or zone protection fault (user violation, write to protected page). |
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261 | | - * If this is just an update of modified status, we do that quickly |
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262 | | - * and exit. Otherwise, we call heavywight functions to do the work. |
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| 178 | + * The other Data TLB exceptions bail out to this point |
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| 179 | + * if they can't resolve the lightweight TLB fault. |
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263 | 180 | */ |
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264 | 181 | START_EXCEPTION(0x0300, DataStorage) |
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265 | | - mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ |
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266 | | - mtspr SPRN_SPRG_SCRATCH1, r11 |
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267 | | -#ifdef CONFIG_403GCX |
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268 | | - stw r12, 0(r0) |
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269 | | - stw r9, 4(r0) |
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270 | | - mfcr r11 |
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271 | | - mfspr r12, SPRN_PID |
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272 | | - stw r11, 8(r0) |
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273 | | - stw r12, 12(r0) |
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274 | | -#else |
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275 | | - mtspr SPRN_SPRG_SCRATCH3, r12 |
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276 | | - mtspr SPRN_SPRG_SCRATCH4, r9 |
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277 | | - mfcr r11 |
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278 | | - mfspr r12, SPRN_PID |
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279 | | - mtspr SPRN_SPRG_SCRATCH6, r11 |
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280 | | - mtspr SPRN_SPRG_SCRATCH5, r12 |
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281 | | -#endif |
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282 | | - |
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283 | | - /* First, check if it was a zone fault (which means a user |
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284 | | - * tried to access a kernel or read-protected page - always |
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285 | | - * a SEGV). All other faults here must be stores, so no |
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286 | | - * need to check ESR_DST as well. */ |
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287 | | - mfspr r10, SPRN_ESR |
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288 | | - andis. r10, r10, ESR_DIZ@h |
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289 | | - bne 2f |
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290 | | - |
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291 | | - mfspr r10, SPRN_DEAR /* Get faulting address */ |
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292 | | - |
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293 | | - /* If we are faulting a kernel address, we have to use the |
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294 | | - * kernel page tables. |
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295 | | - */ |
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296 | | - lis r11, PAGE_OFFSET@h |
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297 | | - cmplw r10, r11 |
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298 | | - blt+ 3f |
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299 | | - lis r11, swapper_pg_dir@h |
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300 | | - ori r11, r11, swapper_pg_dir@l |
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301 | | - li r9, 0 |
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302 | | - mtspr SPRN_PID, r9 /* TLB will have 0 TID */ |
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303 | | - b 4f |
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304 | | - |
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305 | | - /* Get the PGD for the current thread. |
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306 | | - */ |
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307 | | -3: |
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308 | | - mfspr r11,SPRN_SPRG_THREAD |
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309 | | - lwz r11,PGDIR(r11) |
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310 | | -4: |
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311 | | - tophys(r11, r11) |
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312 | | - rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ |
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313 | | - lwz r11, 0(r11) /* Get L1 entry */ |
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314 | | - rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */ |
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315 | | - beq 2f /* Bail if no table */ |
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316 | | - |
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317 | | - rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ |
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318 | | - lwz r11, 0(r12) /* Get Linux PTE */ |
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319 | | - |
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320 | | - andi. r9, r11, _PAGE_RW /* Is it writeable? */ |
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321 | | - beq 2f /* Bail if not */ |
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322 | | - |
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323 | | - /* Update 'changed'. |
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324 | | - */ |
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325 | | - ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE |
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326 | | - stw r11, 0(r12) /* Update Linux page table */ |
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327 | | - |
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328 | | - /* Most of the Linux PTE is ready to load into the TLB LO. |
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329 | | - * We set ZSEL, where only the LS-bit determines user access. |
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330 | | - * We set execute, because we don't have the granularity to |
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331 | | - * properly set this at the page level (Linux problem). |
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332 | | - * If shared is set, we cause a zero PID->TID load. |
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333 | | - * Many of these bits are software only. Bits we don't set |
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334 | | - * here we (properly should) assume have the appropriate value. |
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335 | | - */ |
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336 | | - li r12, 0x0ce2 |
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337 | | - andc r11, r11, r12 /* Make sure 20, 21 are zero */ |
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338 | | - |
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339 | | - /* find the TLB index that caused the fault. It has to be here. |
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340 | | - */ |
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341 | | - tlbsx r9, 0, r10 |
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342 | | - |
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343 | | - tlbwe r11, r9, TLB_DATA /* Load TLB LO */ |
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344 | | - |
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345 | | - /* Done...restore registers and get out of here. |
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346 | | - */ |
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347 | | -#ifdef CONFIG_403GCX |
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348 | | - lwz r12, 12(r0) |
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349 | | - lwz r11, 8(r0) |
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350 | | - mtspr SPRN_PID, r12 |
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351 | | - mtcr r11 |
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352 | | - lwz r9, 4(r0) |
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353 | | - lwz r12, 0(r0) |
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354 | | -#else |
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355 | | - mfspr r12, SPRN_SPRG_SCRATCH5 |
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356 | | - mfspr r11, SPRN_SPRG_SCRATCH6 |
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357 | | - mtspr SPRN_PID, r12 |
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358 | | - mtcr r11 |
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359 | | - mfspr r9, SPRN_SPRG_SCRATCH4 |
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360 | | - mfspr r12, SPRN_SPRG_SCRATCH3 |
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361 | | -#endif |
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362 | | - mfspr r11, SPRN_SPRG_SCRATCH1 |
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363 | | - mfspr r10, SPRN_SPRG_SCRATCH0 |
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364 | | - PPC405_ERR77_SYNC |
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365 | | - rfi /* Should sync shadow TLBs */ |
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366 | | - b . /* prevent prefetch past rfi */ |
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367 | | - |
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368 | | -2: |
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369 | | - /* The bailout. Restore registers to pre-exception conditions |
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370 | | - * and call the heavyweights to help us out. |
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371 | | - */ |
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372 | | -#ifdef CONFIG_403GCX |
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373 | | - lwz r12, 12(r0) |
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374 | | - lwz r11, 8(r0) |
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375 | | - mtspr SPRN_PID, r12 |
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376 | | - mtcr r11 |
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377 | | - lwz r9, 4(r0) |
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378 | | - lwz r12, 0(r0) |
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379 | | -#else |
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380 | | - mfspr r12, SPRN_SPRG_SCRATCH5 |
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381 | | - mfspr r11, SPRN_SPRG_SCRATCH6 |
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382 | | - mtspr SPRN_PID, r12 |
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383 | | - mtcr r11 |
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384 | | - mfspr r9, SPRN_SPRG_SCRATCH4 |
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385 | | - mfspr r12, SPRN_SPRG_SCRATCH3 |
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386 | | -#endif |
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387 | | - mfspr r11, SPRN_SPRG_SCRATCH1 |
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388 | | - mfspr r10, SPRN_SPRG_SCRATCH0 |
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389 | | - b DataAccess |
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| 182 | + EXCEPTION_PROLOG |
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| 183 | + mfspr r5, SPRN_ESR /* Grab the ESR, save it, pass arg3 */ |
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| 184 | + stw r5, _ESR(r11) |
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| 185 | + mfspr r4, SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ |
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| 186 | + stw r4, _DEAR(r11) |
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| 187 | + EXC_XFER_LITE(0x300, handle_page_fault) |
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390 | 188 | |
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391 | 189 | /* |
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392 | 190 | * 0x0400 - Instruction Storage Exception |
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393 | 191 | * This is caused by a fetch from non-execute or guarded pages. |
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394 | 192 | */ |
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395 | 193 | START_EXCEPTION(0x0400, InstructionAccess) |
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396 | | - NORMAL_EXCEPTION_PROLOG |
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| 194 | + EXCEPTION_PROLOG |
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397 | 195 | mr r4,r12 /* Pass SRR0 as arg2 */ |
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| 196 | + stw r4, _DEAR(r11) |
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398 | 197 | li r5,0 /* Pass zero as arg3 */ |
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399 | 198 | EXC_XFER_LITE(0x400, handle_page_fault) |
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400 | 199 | |
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.. | .. |
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403 | 202 | |
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404 | 203 | /* 0x0600 - Alignment Exception */ |
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405 | 204 | START_EXCEPTION(0x0600, Alignment) |
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406 | | - NORMAL_EXCEPTION_PROLOG |
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| 205 | + EXCEPTION_PROLOG |
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407 | 206 | mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */ |
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408 | 207 | stw r4,_DEAR(r11) |
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409 | 208 | addi r3,r1,STACK_FRAME_OVERHEAD |
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410 | | - EXC_XFER_EE(0x600, alignment_exception) |
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| 209 | + EXC_XFER_STD(0x600, alignment_exception) |
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411 | 210 | |
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412 | 211 | /* 0x0700 - Program Exception */ |
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413 | 212 | START_EXCEPTION(0x0700, ProgramCheck) |
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414 | | - NORMAL_EXCEPTION_PROLOG |
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| 213 | + EXCEPTION_PROLOG |
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415 | 214 | mfspr r4,SPRN_ESR /* Grab the ESR and save it */ |
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416 | 215 | stw r4,_ESR(r11) |
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417 | 216 | addi r3,r1,STACK_FRAME_OVERHEAD |
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418 | 217 | EXC_XFER_STD(0x700, program_check_exception) |
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419 | 218 | |
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420 | | - EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE) |
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421 | | - EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE) |
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422 | | - EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE) |
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423 | | - EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE) |
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| 219 | + EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_STD) |
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| 220 | + EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_STD) |
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| 221 | + EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_STD) |
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| 222 | + EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_STD) |
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424 | 223 | |
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425 | 224 | /* 0x0C00 - System Call Exception */ |
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426 | 225 | START_EXCEPTION(0x0C00, SystemCall) |
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427 | | - NORMAL_EXCEPTION_PROLOG |
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428 | | - EXC_XFER_EE_LITE(0xc00, DoSyscall) |
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| 226 | + SYSCALL_ENTRY 0xc00 |
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| 227 | +/* Trap_0D is commented out to get more space for system call exception */ |
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429 | 228 | |
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430 | | - EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE) |
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431 | | - EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE) |
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432 | | - EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE) |
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| 229 | +/* EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_STD) */ |
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| 230 | + EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_STD) |
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| 231 | + EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_STD) |
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433 | 232 | |
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434 | 233 | /* 0x1000 - Programmable Interval Timer (PIT) Exception */ |
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435 | 234 | . = 0x1000 |
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.. | .. |
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453 | 252 | START_EXCEPTION(0x1100, DTLBMiss) |
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454 | 253 | mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ |
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455 | 254 | mtspr SPRN_SPRG_SCRATCH1, r11 |
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456 | | -#ifdef CONFIG_403GCX |
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457 | | - stw r12, 0(r0) |
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458 | | - stw r9, 4(r0) |
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459 | | - mfcr r11 |
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460 | | - mfspr r12, SPRN_PID |
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461 | | - stw r11, 8(r0) |
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462 | | - stw r12, 12(r0) |
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463 | | -#else |
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464 | 255 | mtspr SPRN_SPRG_SCRATCH3, r12 |
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465 | 256 | mtspr SPRN_SPRG_SCRATCH4, r9 |
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466 | | - mfcr r11 |
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467 | | - mfspr r12, SPRN_PID |
---|
468 | | - mtspr SPRN_SPRG_SCRATCH6, r11 |
---|
469 | | - mtspr SPRN_SPRG_SCRATCH5, r12 |
---|
470 | | -#endif |
---|
| 257 | + mfcr r12 |
---|
| 258 | + mfspr r9, SPRN_PID |
---|
| 259 | + mtspr SPRN_SPRG_SCRATCH5, r9 |
---|
471 | 260 | mfspr r10, SPRN_DEAR /* Get faulting address */ |
---|
472 | 261 | |
---|
473 | 262 | /* If we are faulting a kernel address, we have to use the |
---|
.. | .. |
---|
490 | 279 | 4: |
---|
491 | 280 | tophys(r11, r11) |
---|
492 | 281 | rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ |
---|
493 | | - lwz r12, 0(r11) /* Get L1 entry */ |
---|
494 | | - andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ |
---|
| 282 | + lwz r11, 0(r11) /* Get L1 entry */ |
---|
| 283 | + andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */ |
---|
495 | 284 | beq 2f /* Bail if no table */ |
---|
496 | 285 | |
---|
497 | | - rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ |
---|
498 | | - lwz r11, 0(r12) /* Get Linux PTE */ |
---|
499 | | - andi. r9, r11, _PAGE_PRESENT |
---|
500 | | - beq 5f |
---|
| 286 | + rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ |
---|
| 287 | + lwz r11, 0(r11) /* Get Linux PTE */ |
---|
| 288 | + li r9, _PAGE_PRESENT | _PAGE_ACCESSED |
---|
| 289 | + andc. r9, r9, r11 /* Check permission */ |
---|
| 290 | + bne 5f |
---|
501 | 291 | |
---|
502 | | - ori r11, r11, _PAGE_ACCESSED |
---|
503 | | - stw r11, 0(r12) |
---|
| 292 | + rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */ |
---|
| 293 | + and r9, r9, r11 /* hwwrite = dirty & rw */ |
---|
| 294 | + rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */ |
---|
504 | 295 | |
---|
505 | 296 | /* Create TLB tag. This is the faulting address plus a static |
---|
506 | 297 | * set of bits. These are size, valid, E, U0. |
---|
507 | 298 | */ |
---|
508 | | - li r12, 0x00c0 |
---|
509 | | - rlwimi r10, r12, 0, 20, 31 |
---|
| 299 | + li r9, 0x00c0 |
---|
| 300 | + rlwimi r10, r9, 0, 20, 31 |
---|
510 | 301 | |
---|
511 | 302 | b finish_tlb_load |
---|
512 | 303 | |
---|
513 | 304 | 2: /* Check for possible large-page pmd entry */ |
---|
514 | | - rlwinm. r9, r12, 2, 22, 24 |
---|
| 305 | + rlwinm. r9, r11, 2, 22, 24 |
---|
515 | 306 | beq 5f |
---|
516 | 307 | |
---|
517 | 308 | /* Create TLB tag. This is the faulting address, plus a static |
---|
.. | .. |
---|
519 | 310 | */ |
---|
520 | 311 | ori r9, r9, 0x40 |
---|
521 | 312 | rlwimi r10, r9, 0, 20, 31 |
---|
522 | | - mr r11, r12 |
---|
523 | 313 | |
---|
524 | 314 | b finish_tlb_load |
---|
525 | 315 | |
---|
.. | .. |
---|
527 | 317 | /* The bailout. Restore registers to pre-exception conditions |
---|
528 | 318 | * and call the heavyweights to help us out. |
---|
529 | 319 | */ |
---|
530 | | -#ifdef CONFIG_403GCX |
---|
531 | | - lwz r12, 12(r0) |
---|
532 | | - lwz r11, 8(r0) |
---|
533 | | - mtspr SPRN_PID, r12 |
---|
534 | | - mtcr r11 |
---|
535 | | - lwz r9, 4(r0) |
---|
536 | | - lwz r12, 0(r0) |
---|
537 | | -#else |
---|
538 | | - mfspr r12, SPRN_SPRG_SCRATCH5 |
---|
539 | | - mfspr r11, SPRN_SPRG_SCRATCH6 |
---|
540 | | - mtspr SPRN_PID, r12 |
---|
541 | | - mtcr r11 |
---|
| 320 | + mfspr r9, SPRN_SPRG_SCRATCH5 |
---|
| 321 | + mtspr SPRN_PID, r9 |
---|
| 322 | + mtcr r12 |
---|
542 | 323 | mfspr r9, SPRN_SPRG_SCRATCH4 |
---|
543 | 324 | mfspr r12, SPRN_SPRG_SCRATCH3 |
---|
544 | | -#endif |
---|
545 | 325 | mfspr r11, SPRN_SPRG_SCRATCH1 |
---|
546 | 326 | mfspr r10, SPRN_SPRG_SCRATCH0 |
---|
547 | | - b DataAccess |
---|
| 327 | + b DataStorage |
---|
548 | 328 | |
---|
549 | 329 | /* 0x1200 - Instruction TLB Miss Exception |
---|
550 | 330 | * Nearly the same as above, except we get our information from different |
---|
.. | .. |
---|
553 | 333 | START_EXCEPTION(0x1200, ITLBMiss) |
---|
554 | 334 | mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */ |
---|
555 | 335 | mtspr SPRN_SPRG_SCRATCH1, r11 |
---|
556 | | -#ifdef CONFIG_403GCX |
---|
557 | | - stw r12, 0(r0) |
---|
558 | | - stw r9, 4(r0) |
---|
559 | | - mfcr r11 |
---|
560 | | - mfspr r12, SPRN_PID |
---|
561 | | - stw r11, 8(r0) |
---|
562 | | - stw r12, 12(r0) |
---|
563 | | -#else |
---|
564 | 336 | mtspr SPRN_SPRG_SCRATCH3, r12 |
---|
565 | 337 | mtspr SPRN_SPRG_SCRATCH4, r9 |
---|
566 | | - mfcr r11 |
---|
567 | | - mfspr r12, SPRN_PID |
---|
568 | | - mtspr SPRN_SPRG_SCRATCH6, r11 |
---|
569 | | - mtspr SPRN_SPRG_SCRATCH5, r12 |
---|
570 | | -#endif |
---|
| 338 | + mfcr r12 |
---|
| 339 | + mfspr r9, SPRN_PID |
---|
| 340 | + mtspr SPRN_SPRG_SCRATCH5, r9 |
---|
571 | 341 | mfspr r10, SPRN_SRR0 /* Get faulting address */ |
---|
572 | 342 | |
---|
573 | 343 | /* If we are faulting a kernel address, we have to use the |
---|
.. | .. |
---|
590 | 360 | 4: |
---|
591 | 361 | tophys(r11, r11) |
---|
592 | 362 | rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */ |
---|
593 | | - lwz r12, 0(r11) /* Get L1 entry */ |
---|
594 | | - andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */ |
---|
| 363 | + lwz r11, 0(r11) /* Get L1 entry */ |
---|
| 364 | + andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */ |
---|
595 | 365 | beq 2f /* Bail if no table */ |
---|
596 | 366 | |
---|
597 | | - rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */ |
---|
598 | | - lwz r11, 0(r12) /* Get Linux PTE */ |
---|
599 | | - andi. r9, r11, _PAGE_PRESENT |
---|
600 | | - beq 5f |
---|
| 367 | + rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */ |
---|
| 368 | + lwz r11, 0(r11) /* Get Linux PTE */ |
---|
| 369 | + li r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC |
---|
| 370 | + andc. r9, r9, r11 /* Check permission */ |
---|
| 371 | + bne 5f |
---|
601 | 372 | |
---|
602 | | - ori r11, r11, _PAGE_ACCESSED |
---|
603 | | - stw r11, 0(r12) |
---|
| 373 | + rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */ |
---|
| 374 | + and r9, r9, r11 /* hwwrite = dirty & rw */ |
---|
| 375 | + rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */ |
---|
604 | 376 | |
---|
605 | 377 | /* Create TLB tag. This is the faulting address plus a static |
---|
606 | 378 | * set of bits. These are size, valid, E, U0. |
---|
607 | 379 | */ |
---|
608 | | - li r12, 0x00c0 |
---|
609 | | - rlwimi r10, r12, 0, 20, 31 |
---|
| 380 | + li r9, 0x00c0 |
---|
| 381 | + rlwimi r10, r9, 0, 20, 31 |
---|
610 | 382 | |
---|
611 | 383 | b finish_tlb_load |
---|
612 | 384 | |
---|
613 | 385 | 2: /* Check for possible large-page pmd entry */ |
---|
614 | | - rlwinm. r9, r12, 2, 22, 24 |
---|
| 386 | + rlwinm. r9, r11, 2, 22, 24 |
---|
615 | 387 | beq 5f |
---|
616 | 388 | |
---|
617 | 389 | /* Create TLB tag. This is the faulting address, plus a static |
---|
.. | .. |
---|
619 | 391 | */ |
---|
620 | 392 | ori r9, r9, 0x40 |
---|
621 | 393 | rlwimi r10, r9, 0, 20, 31 |
---|
622 | | - mr r11, r12 |
---|
623 | 394 | |
---|
624 | 395 | b finish_tlb_load |
---|
625 | 396 | |
---|
.. | .. |
---|
627 | 398 | /* The bailout. Restore registers to pre-exception conditions |
---|
628 | 399 | * and call the heavyweights to help us out. |
---|
629 | 400 | */ |
---|
630 | | -#ifdef CONFIG_403GCX |
---|
631 | | - lwz r12, 12(r0) |
---|
632 | | - lwz r11, 8(r0) |
---|
633 | | - mtspr SPRN_PID, r12 |
---|
634 | | - mtcr r11 |
---|
635 | | - lwz r9, 4(r0) |
---|
636 | | - lwz r12, 0(r0) |
---|
637 | | -#else |
---|
638 | | - mfspr r12, SPRN_SPRG_SCRATCH5 |
---|
639 | | - mfspr r11, SPRN_SPRG_SCRATCH6 |
---|
640 | | - mtspr SPRN_PID, r12 |
---|
641 | | - mtcr r11 |
---|
| 401 | + mfspr r9, SPRN_SPRG_SCRATCH5 |
---|
| 402 | + mtspr SPRN_PID, r9 |
---|
| 403 | + mtcr r12 |
---|
642 | 404 | mfspr r9, SPRN_SPRG_SCRATCH4 |
---|
643 | 405 | mfspr r12, SPRN_SPRG_SCRATCH3 |
---|
644 | | -#endif |
---|
645 | 406 | mfspr r11, SPRN_SPRG_SCRATCH1 |
---|
646 | 407 | mfspr r10, SPRN_SPRG_SCRATCH0 |
---|
647 | 408 | b InstructionAccess |
---|
648 | 409 | |
---|
649 | | - EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE) |
---|
650 | | - EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE) |
---|
651 | | - EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) |
---|
652 | | - EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) |
---|
653 | | -#ifdef CONFIG_IBM405_ERR51 |
---|
654 | | - /* 405GP errata 51 */ |
---|
655 | | - START_EXCEPTION(0x1700, Trap_17) |
---|
656 | | - b DTLBMiss |
---|
657 | | -#else |
---|
658 | | - EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) |
---|
659 | | -#endif |
---|
660 | | - EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) |
---|
661 | | - EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) |
---|
662 | | - EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE) |
---|
663 | | - EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE) |
---|
664 | | - EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE) |
---|
665 | | - EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE) |
---|
666 | | - EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE) |
---|
667 | | - EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE) |
---|
| 410 | + EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD) |
---|
| 411 | + EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_STD) |
---|
| 412 | + EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD) |
---|
| 413 | + EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_STD) |
---|
| 414 | + EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_STD) |
---|
| 415 | + EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD) |
---|
| 416 | + EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD) |
---|
| 417 | + EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_STD) |
---|
| 418 | + EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_STD) |
---|
| 419 | + EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_STD) |
---|
| 420 | + EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_STD) |
---|
| 421 | + EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_STD) |
---|
| 422 | + EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_STD) |
---|
668 | 423 | |
---|
669 | 424 | /* Check for a single step debug exception while in an exception |
---|
670 | 425 | * handler before state has been saved. This is to catch the case |
---|
.. | .. |
---|
717 | 472 | lwz r12,GPR12(r11) |
---|
718 | 473 | lwz r10,crit_r10@l(0) |
---|
719 | 474 | lwz r11,crit_r11@l(0) |
---|
720 | | - PPC405_ERR77_SYNC |
---|
721 | 475 | rfci |
---|
722 | 476 | b . |
---|
723 | 477 | |
---|
.. | .. |
---|
726 | 480 | addi r3,r1,STACK_FRAME_OVERHEAD |
---|
727 | 481 | EXC_XFER_TEMPLATE(DebugException, 0x2002, \ |
---|
728 | 482 | (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ |
---|
729 | | - NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) |
---|
| 483 | + crit_transfer_to_handler, ret_from_crit_exc) |
---|
730 | 484 | |
---|
731 | 485 | /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */ |
---|
732 | 486 | Decrementer: |
---|
733 | | - NORMAL_EXCEPTION_PROLOG |
---|
| 487 | + EXCEPTION_PROLOG |
---|
734 | 488 | lis r0,TSR_PIS@h |
---|
735 | 489 | mtspr SPRN_TSR,r0 /* Clear the PIT exception */ |
---|
736 | 490 | addi r3,r1,STACK_FRAME_OVERHEAD |
---|
.. | .. |
---|
738 | 492 | |
---|
739 | 493 | /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */ |
---|
740 | 494 | FITException: |
---|
741 | | - NORMAL_EXCEPTION_PROLOG |
---|
| 495 | + EXCEPTION_PROLOG |
---|
742 | 496 | addi r3,r1,STACK_FRAME_OVERHEAD; |
---|
743 | | - EXC_XFER_EE(0x1010, unknown_exception) |
---|
| 497 | + EXC_XFER_STD(0x1010, unknown_exception) |
---|
744 | 498 | |
---|
745 | 499 | /* Watchdog Timer (WDT) Exception. (from 0x1020) */ |
---|
746 | 500 | WDTException: |
---|
.. | .. |
---|
748 | 502 | addi r3,r1,STACK_FRAME_OVERHEAD; |
---|
749 | 503 | EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2, |
---|
750 | 504 | (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), |
---|
751 | | - NOCOPY, crit_transfer_to_handler, |
---|
752 | | - ret_from_crit_exc) |
---|
753 | | - |
---|
754 | | -/* |
---|
755 | | - * The other Data TLB exceptions bail out to this point |
---|
756 | | - * if they can't resolve the lightweight TLB fault. |
---|
757 | | - */ |
---|
758 | | -DataAccess: |
---|
759 | | - NORMAL_EXCEPTION_PROLOG |
---|
760 | | - mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ |
---|
761 | | - stw r5,_ESR(r11) |
---|
762 | | - mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ |
---|
763 | | - EXC_XFER_LITE(0x300, handle_page_fault) |
---|
| 505 | + crit_transfer_to_handler, ret_from_crit_exc) |
---|
764 | 506 | |
---|
765 | 507 | /* Other PowerPC processors, namely those derived from the 6xx-series |
---|
766 | 508 | * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved. |
---|
.. | .. |
---|
773 | 515 | * miss get to this point to load the TLB. |
---|
774 | 516 | * r10 - TLB_TAG value |
---|
775 | 517 | * r11 - Linux PTE |
---|
776 | | - * r12, r9 - available to use |
---|
| 518 | + * r9 - available to use |
---|
777 | 519 | * PID - loaded with proper value when we get here |
---|
778 | 520 | * Upon exit, we reload everything and RFI. |
---|
779 | 521 | * Actually, it will fit now, but oh well.....a common place |
---|
.. | .. |
---|
782 | 524 | tlb_4xx_index: |
---|
783 | 525 | .long 0 |
---|
784 | 526 | finish_tlb_load: |
---|
785 | | - /* load the next available TLB index. |
---|
786 | | - */ |
---|
787 | | - lwz r9, tlb_4xx_index@l(0) |
---|
788 | | - addi r9, r9, 1 |
---|
789 | | - andi. r9, r9, (PPC40X_TLB_SIZE-1) |
---|
790 | | - stw r9, tlb_4xx_index@l(0) |
---|
791 | | - |
---|
792 | | -6: |
---|
793 | 527 | /* |
---|
794 | 528 | * Clear out the software-only bits in the PTE to generate the |
---|
795 | 529 | * TLB_DATA value. These are the bottom 2 bits of the RPM, the |
---|
796 | 530 | * top 3 bits of the zone field, and M. |
---|
797 | 531 | */ |
---|
798 | | - li r12, 0x0ce2 |
---|
799 | | - andc r11, r11, r12 |
---|
| 532 | + li r9, 0x0ce2 |
---|
| 533 | + andc r11, r11, r9 |
---|
| 534 | + |
---|
| 535 | + /* load the next available TLB index. */ |
---|
| 536 | + lwz r9, tlb_4xx_index@l(0) |
---|
| 537 | + addi r9, r9, 1 |
---|
| 538 | + andi. r9, r9, PPC40X_TLB_SIZE - 1 |
---|
| 539 | + stw r9, tlb_4xx_index@l(0) |
---|
800 | 540 | |
---|
801 | 541 | tlbwe r11, r9, TLB_DATA /* Load TLB LO */ |
---|
802 | 542 | tlbwe r10, r9, TLB_TAG /* Load TLB HI */ |
---|
803 | 543 | |
---|
804 | 544 | /* Done...restore registers and get out of here. |
---|
805 | 545 | */ |
---|
806 | | -#ifdef CONFIG_403GCX |
---|
807 | | - lwz r12, 12(r0) |
---|
808 | | - lwz r11, 8(r0) |
---|
809 | | - mtspr SPRN_PID, r12 |
---|
810 | | - mtcr r11 |
---|
811 | | - lwz r9, 4(r0) |
---|
812 | | - lwz r12, 0(r0) |
---|
813 | | -#else |
---|
814 | | - mfspr r12, SPRN_SPRG_SCRATCH5 |
---|
815 | | - mfspr r11, SPRN_SPRG_SCRATCH6 |
---|
816 | | - mtspr SPRN_PID, r12 |
---|
817 | | - mtcr r11 |
---|
| 546 | + mfspr r9, SPRN_SPRG_SCRATCH5 |
---|
| 547 | + mtspr SPRN_PID, r9 |
---|
| 548 | + mtcr r12 |
---|
818 | 549 | mfspr r9, SPRN_SPRG_SCRATCH4 |
---|
819 | 550 | mfspr r12, SPRN_SPRG_SCRATCH3 |
---|
820 | | -#endif |
---|
821 | 551 | mfspr r11, SPRN_SPRG_SCRATCH1 |
---|
822 | 552 | mfspr r10, SPRN_SPRG_SCRATCH0 |
---|
823 | | - PPC405_ERR77_SYNC |
---|
824 | 553 | rfi /* Should sync shadow TLBs */ |
---|
825 | 554 | b . /* prevent prefetch past rfi */ |
---|
826 | 555 | |
---|
.. | .. |
---|
848 | 577 | /* |
---|
849 | 578 | * Decide what sort of machine this is and initialize the MMU. |
---|
850 | 579 | */ |
---|
| 580 | +#ifdef CONFIG_KASAN |
---|
| 581 | + bl kasan_early_init |
---|
| 582 | +#endif |
---|
851 | 583 | li r3,0 |
---|
852 | 584 | mr r4,r31 |
---|
853 | 585 | bl machine_init |
---|
.. | .. |
---|
880 | 612 | ori r6, r6, swapper_pg_dir@l |
---|
881 | 613 | lis r5, abatron_pteptrs@h |
---|
882 | 614 | ori r5, r5, abatron_pteptrs@l |
---|
883 | | - stw r5, 0xf0(r0) /* Must match your Abatron config file */ |
---|
| 615 | + stw r5, 0xf0(0) /* Must match your Abatron config file */ |
---|
884 | 616 | tophys(r5,r5) |
---|
885 | 617 | stw r6, 0(r5) |
---|
886 | 618 | |
---|
.. | .. |
---|
895 | 627 | b . /* prevent prefetch past rfi */ |
---|
896 | 628 | |
---|
897 | 629 | /* Set up the initial MMU state so we can do the first level of |
---|
898 | | - * kernel initialization. This maps the first 16 MBytes of memory 1:1 |
---|
| 630 | + * kernel initialization. This maps the first 32 MBytes of memory 1:1 |
---|
899 | 631 | * virtual to physical and more importantly sets the cache mode. |
---|
900 | 632 | */ |
---|
901 | 633 | initial_mmu: |
---|
.. | .. |
---|
932 | 664 | tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ |
---|
933 | 665 | tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ |
---|
934 | 666 | |
---|
| 667 | + li r0,62 /* TLB slot 62 */ |
---|
| 668 | + addis r4,r4,SZ_16M@h |
---|
| 669 | + addis r3,r3,SZ_16M@h |
---|
| 670 | + tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */ |
---|
| 671 | + tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */ |
---|
| 672 | + |
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935 | 673 | isync |
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936 | 674 | |
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937 | 675 | /* Establish the exception vector base |
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.. | .. |
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953 | 691 | /* Context switch the PTE pointer for the Abatron BDI2000. |
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954 | 692 | * The PGDIR is the second parameter. |
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955 | 693 | */ |
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956 | | - lis r5, KERNELBASE@h |
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957 | | - lwz r5, 0xf0(r5) |
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958 | | - stw r4, 0x4(r5) |
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| 694 | + lis r5, abatron_pteptrs@ha |
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| 695 | + stw r4, abatron_pteptrs@l + 0x4(r5) |
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959 | 696 | #endif |
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960 | 697 | sync |
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961 | 698 | mtspr SPRN_PID,r3 |
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