hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/powerpc/kernel/head_40x.S
....@@ -1,3 +1,4 @@
1
+/* SPDX-License-Identifier: GPL-2.0-or-later */
12 /*
23 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
34 * Initial PowerPC version.
....@@ -18,31 +19,26 @@
1819 * frank_rowand@mvista.com or source@mvista.com
1920 * debbie_chu@mvista.com
2021 *
21
- *
2222 * Module name: head_4xx.S
2323 *
2424 * Description:
2525 * Kernel execution entry point code.
26
- *
27
- * This program is free software; you can redistribute it and/or
28
- * modify it under the terms of the GNU General Public License
29
- * as published by the Free Software Foundation; either version
30
- * 2 of the License, or (at your option) any later version.
31
- *
3226 */
3327
3428 #include <linux/init.h>
29
+#include <linux/pgtable.h>
30
+#include <linux/sizes.h>
3531 #include <asm/processor.h>
3632 #include <asm/page.h>
3733 #include <asm/mmu.h>
38
-#include <asm/pgtable.h>
3934 #include <asm/cputable.h>
4035 #include <asm/thread_info.h>
4136 #include <asm/ppc_asm.h>
4237 #include <asm/asm-offsets.h>
4338 #include <asm/ptrace.h>
4439 #include <asm/export.h>
45
-#include <asm/asm-405.h>
40
+
41
+#include "head_32.h"
4642
4743 /* As with the other PowerPC ports, it is expected that when code
4844 * execution begins here, the following registers contain valid, yet
....@@ -77,7 +73,6 @@
7773 lis r0,start_here@h
7874 ori r0,r0,start_here@l
7975 mtspr SPRN_SRR0,r0
80
- SYNC
8176 rfi /* enables MMU */
8277 b . /* prevent prefetch past rfi */
8378
....@@ -99,46 +94,6 @@
9994 .space 4
10095
10196 /*
102
- * Exception vector entry code. This code runs with address translation
103
- * turned off (i.e. using physical addresses). We assume SPRG_THREAD has
104
- * the physical address of the current task thread_struct.
105
- * Note that we have to have decremented r1 before we write to any fields
106
- * of the exception frame, since a critical interrupt could occur at any
107
- * time, and it will write to the area immediately below the current r1.
108
- */
109
-#define NORMAL_EXCEPTION_PROLOG \
110
- mtspr SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\
111
- mtspr SPRN_SPRG_SCRATCH1,r11; \
112
- mtspr SPRN_SPRG_SCRATCH2,r1; \
113
- mfcr r10; /* save CR in r10 for now */\
114
- mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
115
- andi. r11,r11,MSR_PR; \
116
- beq 1f; \
117
- mfspr r1,SPRN_SPRG_THREAD; /* if from user, start at top of */\
118
- lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
119
- addi r1,r1,THREAD_SIZE; \
120
-1: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
121
- tophys(r11,r1); \
122
- stw r10,_CCR(r11); /* save various registers */\
123
- stw r12,GPR12(r11); \
124
- stw r9,GPR9(r11); \
125
- mfspr r10,SPRN_SPRG_SCRATCH0; \
126
- stw r10,GPR10(r11); \
127
- mfspr r12,SPRN_SPRG_SCRATCH1; \
128
- stw r12,GPR11(r11); \
129
- mflr r10; \
130
- stw r10,_LINK(r11); \
131
- mfspr r10,SPRN_SPRG_SCRATCH2; \
132
- mfspr r12,SPRN_SRR0; \
133
- stw r10,GPR1(r11); \
134
- mfspr r9,SPRN_SRR1; \
135
- stw r10,0(r11); \
136
- rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
137
- stw r0,GPR0(r11); \
138
- SAVE_4GPRS(3, r11); \
139
- SAVE_2GPRS(7, r11)
140
-
141
-/*
14297 * Exception prolog for critical exceptions. This is a little different
14398 * from the normal exception prolog above since a critical exception
14499 * can potentially occur at any point during normal exception processing.
....@@ -158,7 +113,7 @@
158113 beq 1f; \
159114 /* COMING FROM USER MODE */ \
160115 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
161
- lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
116
+ lwz r11,TASK_STACK-THREAD(r11); /* this thread's kernel stack */\
162117 1: addi r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm */\
163118 tophys(r11,r11); \
164119 stw r10,_CCR(r11); /* save various registers */\
....@@ -177,6 +132,9 @@
177132 tovirt(r1,r11); \
178133 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
179134 stw r0,GPR0(r11); \
135
+ lis r10, STACK_FRAME_REGS_MARKER@ha; /* exception frame marker */\
136
+ addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
137
+ stw r10, 8(r11); \
180138 SAVE_4GPRS(3, r11); \
181139 SAVE_2GPRS(7, r11)
182140
....@@ -196,53 +154,12 @@
196154 /*
197155 * Exception vectors.
198156 */
199
-#define START_EXCEPTION(n, label) \
200
- . = n; \
201
-label:
202
-
203
-#define EXCEPTION(n, label, hdlr, xfer) \
204
- START_EXCEPTION(n, label); \
205
- NORMAL_EXCEPTION_PROLOG; \
206
- addi r3,r1,STACK_FRAME_OVERHEAD; \
207
- xfer(n, hdlr)
208
-
209157 #define CRITICAL_EXCEPTION(n, label, hdlr) \
210158 START_EXCEPTION(n, label); \
211159 CRITICAL_EXCEPTION_PROLOG; \
212160 addi r3,r1,STACK_FRAME_OVERHEAD; \
213161 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
214
- NOCOPY, crit_transfer_to_handler, \
215
- ret_from_crit_exc)
216
-
217
-#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
218
- li r10,trap; \
219
- stw r10,_TRAP(r11); \
220
- lis r10,msr@h; \
221
- ori r10,r10,msr@l; \
222
- copyee(r10, r9); \
223
- bl tfer; \
224
- .long hdlr; \
225
- .long ret
226
-
227
-#define COPY_EE(d, s) rlwimi d,s,0,16,16
228
-#define NOCOPY(d, s)
229
-
230
-#define EXC_XFER_STD(n, hdlr) \
231
- EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
232
- ret_from_except_full)
233
-
234
-#define EXC_XFER_LITE(n, hdlr) \
235
- EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
236
- ret_from_except)
237
-
238
-#define EXC_XFER_EE(n, hdlr) \
239
- EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
240
- ret_from_except_full)
241
-
242
-#define EXC_XFER_EE_LITE(n, hdlr) \
243
- EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
244
- ret_from_except)
245
-
162
+ crit_transfer_to_handler, ret_from_crit_exc)
246163
247164 /*
248165 * 0x0100 - Critical Interrupt Exception
....@@ -258,143 +175,25 @@
258175 * 0x0300 - Data Storage Exception
259176 * This happens for just a few reasons. U0 set (but we don't do that),
260177 * or zone protection fault (user violation, write to protected page).
261
- * If this is just an update of modified status, we do that quickly
262
- * and exit. Otherwise, we call heavywight functions to do the work.
178
+ * The other Data TLB exceptions bail out to this point
179
+ * if they can't resolve the lightweight TLB fault.
263180 */
264181 START_EXCEPTION(0x0300, DataStorage)
265
- mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
266
- mtspr SPRN_SPRG_SCRATCH1, r11
267
-#ifdef CONFIG_403GCX
268
- stw r12, 0(r0)
269
- stw r9, 4(r0)
270
- mfcr r11
271
- mfspr r12, SPRN_PID
272
- stw r11, 8(r0)
273
- stw r12, 12(r0)
274
-#else
275
- mtspr SPRN_SPRG_SCRATCH3, r12
276
- mtspr SPRN_SPRG_SCRATCH4, r9
277
- mfcr r11
278
- mfspr r12, SPRN_PID
279
- mtspr SPRN_SPRG_SCRATCH6, r11
280
- mtspr SPRN_SPRG_SCRATCH5, r12
281
-#endif
282
-
283
- /* First, check if it was a zone fault (which means a user
284
- * tried to access a kernel or read-protected page - always
285
- * a SEGV). All other faults here must be stores, so no
286
- * need to check ESR_DST as well. */
287
- mfspr r10, SPRN_ESR
288
- andis. r10, r10, ESR_DIZ@h
289
- bne 2f
290
-
291
- mfspr r10, SPRN_DEAR /* Get faulting address */
292
-
293
- /* If we are faulting a kernel address, we have to use the
294
- * kernel page tables.
295
- */
296
- lis r11, PAGE_OFFSET@h
297
- cmplw r10, r11
298
- blt+ 3f
299
- lis r11, swapper_pg_dir@h
300
- ori r11, r11, swapper_pg_dir@l
301
- li r9, 0
302
- mtspr SPRN_PID, r9 /* TLB will have 0 TID */
303
- b 4f
304
-
305
- /* Get the PGD for the current thread.
306
- */
307
-3:
308
- mfspr r11,SPRN_SPRG_THREAD
309
- lwz r11,PGDIR(r11)
310
-4:
311
- tophys(r11, r11)
312
- rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
313
- lwz r11, 0(r11) /* Get L1 entry */
314
- rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
315
- beq 2f /* Bail if no table */
316
-
317
- rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
318
- lwz r11, 0(r12) /* Get Linux PTE */
319
-
320
- andi. r9, r11, _PAGE_RW /* Is it writeable? */
321
- beq 2f /* Bail if not */
322
-
323
- /* Update 'changed'.
324
- */
325
- ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
326
- stw r11, 0(r12) /* Update Linux page table */
327
-
328
- /* Most of the Linux PTE is ready to load into the TLB LO.
329
- * We set ZSEL, where only the LS-bit determines user access.
330
- * We set execute, because we don't have the granularity to
331
- * properly set this at the page level (Linux problem).
332
- * If shared is set, we cause a zero PID->TID load.
333
- * Many of these bits are software only. Bits we don't set
334
- * here we (properly should) assume have the appropriate value.
335
- */
336
- li r12, 0x0ce2
337
- andc r11, r11, r12 /* Make sure 20, 21 are zero */
338
-
339
- /* find the TLB index that caused the fault. It has to be here.
340
- */
341
- tlbsx r9, 0, r10
342
-
343
- tlbwe r11, r9, TLB_DATA /* Load TLB LO */
344
-
345
- /* Done...restore registers and get out of here.
346
- */
347
-#ifdef CONFIG_403GCX
348
- lwz r12, 12(r0)
349
- lwz r11, 8(r0)
350
- mtspr SPRN_PID, r12
351
- mtcr r11
352
- lwz r9, 4(r0)
353
- lwz r12, 0(r0)
354
-#else
355
- mfspr r12, SPRN_SPRG_SCRATCH5
356
- mfspr r11, SPRN_SPRG_SCRATCH6
357
- mtspr SPRN_PID, r12
358
- mtcr r11
359
- mfspr r9, SPRN_SPRG_SCRATCH4
360
- mfspr r12, SPRN_SPRG_SCRATCH3
361
-#endif
362
- mfspr r11, SPRN_SPRG_SCRATCH1
363
- mfspr r10, SPRN_SPRG_SCRATCH0
364
- PPC405_ERR77_SYNC
365
- rfi /* Should sync shadow TLBs */
366
- b . /* prevent prefetch past rfi */
367
-
368
-2:
369
- /* The bailout. Restore registers to pre-exception conditions
370
- * and call the heavyweights to help us out.
371
- */
372
-#ifdef CONFIG_403GCX
373
- lwz r12, 12(r0)
374
- lwz r11, 8(r0)
375
- mtspr SPRN_PID, r12
376
- mtcr r11
377
- lwz r9, 4(r0)
378
- lwz r12, 0(r0)
379
-#else
380
- mfspr r12, SPRN_SPRG_SCRATCH5
381
- mfspr r11, SPRN_SPRG_SCRATCH6
382
- mtspr SPRN_PID, r12
383
- mtcr r11
384
- mfspr r9, SPRN_SPRG_SCRATCH4
385
- mfspr r12, SPRN_SPRG_SCRATCH3
386
-#endif
387
- mfspr r11, SPRN_SPRG_SCRATCH1
388
- mfspr r10, SPRN_SPRG_SCRATCH0
389
- b DataAccess
182
+ EXCEPTION_PROLOG
183
+ mfspr r5, SPRN_ESR /* Grab the ESR, save it, pass arg3 */
184
+ stw r5, _ESR(r11)
185
+ mfspr r4, SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
186
+ stw r4, _DEAR(r11)
187
+ EXC_XFER_LITE(0x300, handle_page_fault)
390188
391189 /*
392190 * 0x0400 - Instruction Storage Exception
393191 * This is caused by a fetch from non-execute or guarded pages.
394192 */
395193 START_EXCEPTION(0x0400, InstructionAccess)
396
- NORMAL_EXCEPTION_PROLOG
194
+ EXCEPTION_PROLOG
397195 mr r4,r12 /* Pass SRR0 as arg2 */
196
+ stw r4, _DEAR(r11)
398197 li r5,0 /* Pass zero as arg3 */
399198 EXC_XFER_LITE(0x400, handle_page_fault)
400199
....@@ -403,33 +202,33 @@
403202
404203 /* 0x0600 - Alignment Exception */
405204 START_EXCEPTION(0x0600, Alignment)
406
- NORMAL_EXCEPTION_PROLOG
205
+ EXCEPTION_PROLOG
407206 mfspr r4,SPRN_DEAR /* Grab the DEAR and save it */
408207 stw r4,_DEAR(r11)
409208 addi r3,r1,STACK_FRAME_OVERHEAD
410
- EXC_XFER_EE(0x600, alignment_exception)
209
+ EXC_XFER_STD(0x600, alignment_exception)
411210
412211 /* 0x0700 - Program Exception */
413212 START_EXCEPTION(0x0700, ProgramCheck)
414
- NORMAL_EXCEPTION_PROLOG
213
+ EXCEPTION_PROLOG
415214 mfspr r4,SPRN_ESR /* Grab the ESR and save it */
416215 stw r4,_ESR(r11)
417216 addi r3,r1,STACK_FRAME_OVERHEAD
418217 EXC_XFER_STD(0x700, program_check_exception)
419218
420
- EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE)
421
- EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE)
422
- EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE)
423
- EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE)
219
+ EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_STD)
220
+ EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_STD)
221
+ EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_STD)
222
+ EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_STD)
424223
425224 /* 0x0C00 - System Call Exception */
426225 START_EXCEPTION(0x0C00, SystemCall)
427
- NORMAL_EXCEPTION_PROLOG
428
- EXC_XFER_EE_LITE(0xc00, DoSyscall)
226
+ SYSCALL_ENTRY 0xc00
227
+/* Trap_0D is commented out to get more space for system call exception */
429228
430
- EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE)
431
- EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE)
432
- EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE)
229
+/* EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_STD) */
230
+ EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_STD)
231
+ EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_STD)
433232
434233 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
435234 . = 0x1000
....@@ -453,21 +252,11 @@
453252 START_EXCEPTION(0x1100, DTLBMiss)
454253 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
455254 mtspr SPRN_SPRG_SCRATCH1, r11
456
-#ifdef CONFIG_403GCX
457
- stw r12, 0(r0)
458
- stw r9, 4(r0)
459
- mfcr r11
460
- mfspr r12, SPRN_PID
461
- stw r11, 8(r0)
462
- stw r12, 12(r0)
463
-#else
464255 mtspr SPRN_SPRG_SCRATCH3, r12
465256 mtspr SPRN_SPRG_SCRATCH4, r9
466
- mfcr r11
467
- mfspr r12, SPRN_PID
468
- mtspr SPRN_SPRG_SCRATCH6, r11
469
- mtspr SPRN_SPRG_SCRATCH5, r12
470
-#endif
257
+ mfcr r12
258
+ mfspr r9, SPRN_PID
259
+ mtspr SPRN_SPRG_SCRATCH5, r9
471260 mfspr r10, SPRN_DEAR /* Get faulting address */
472261
473262 /* If we are faulting a kernel address, we have to use the
....@@ -490,28 +279,30 @@
490279 4:
491280 tophys(r11, r11)
492281 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
493
- lwz r12, 0(r11) /* Get L1 entry */
494
- andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */
282
+ lwz r11, 0(r11) /* Get L1 entry */
283
+ andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */
495284 beq 2f /* Bail if no table */
496285
497
- rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
498
- lwz r11, 0(r12) /* Get Linux PTE */
499
- andi. r9, r11, _PAGE_PRESENT
500
- beq 5f
286
+ rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
287
+ lwz r11, 0(r11) /* Get Linux PTE */
288
+ li r9, _PAGE_PRESENT | _PAGE_ACCESSED
289
+ andc. r9, r9, r11 /* Check permission */
290
+ bne 5f
501291
502
- ori r11, r11, _PAGE_ACCESSED
503
- stw r11, 0(r12)
292
+ rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */
293
+ and r9, r9, r11 /* hwwrite = dirty & rw */
294
+ rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */
504295
505296 /* Create TLB tag. This is the faulting address plus a static
506297 * set of bits. These are size, valid, E, U0.
507298 */
508
- li r12, 0x00c0
509
- rlwimi r10, r12, 0, 20, 31
299
+ li r9, 0x00c0
300
+ rlwimi r10, r9, 0, 20, 31
510301
511302 b finish_tlb_load
512303
513304 2: /* Check for possible large-page pmd entry */
514
- rlwinm. r9, r12, 2, 22, 24
305
+ rlwinm. r9, r11, 2, 22, 24
515306 beq 5f
516307
517308 /* Create TLB tag. This is the faulting address, plus a static
....@@ -519,7 +310,6 @@
519310 */
520311 ori r9, r9, 0x40
521312 rlwimi r10, r9, 0, 20, 31
522
- mr r11, r12
523313
524314 b finish_tlb_load
525315
....@@ -527,24 +317,14 @@
527317 /* The bailout. Restore registers to pre-exception conditions
528318 * and call the heavyweights to help us out.
529319 */
530
-#ifdef CONFIG_403GCX
531
- lwz r12, 12(r0)
532
- lwz r11, 8(r0)
533
- mtspr SPRN_PID, r12
534
- mtcr r11
535
- lwz r9, 4(r0)
536
- lwz r12, 0(r0)
537
-#else
538
- mfspr r12, SPRN_SPRG_SCRATCH5
539
- mfspr r11, SPRN_SPRG_SCRATCH6
540
- mtspr SPRN_PID, r12
541
- mtcr r11
320
+ mfspr r9, SPRN_SPRG_SCRATCH5
321
+ mtspr SPRN_PID, r9
322
+ mtcr r12
542323 mfspr r9, SPRN_SPRG_SCRATCH4
543324 mfspr r12, SPRN_SPRG_SCRATCH3
544
-#endif
545325 mfspr r11, SPRN_SPRG_SCRATCH1
546326 mfspr r10, SPRN_SPRG_SCRATCH0
547
- b DataAccess
327
+ b DataStorage
548328
549329 /* 0x1200 - Instruction TLB Miss Exception
550330 * Nearly the same as above, except we get our information from different
....@@ -553,21 +333,11 @@
553333 START_EXCEPTION(0x1200, ITLBMiss)
554334 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
555335 mtspr SPRN_SPRG_SCRATCH1, r11
556
-#ifdef CONFIG_403GCX
557
- stw r12, 0(r0)
558
- stw r9, 4(r0)
559
- mfcr r11
560
- mfspr r12, SPRN_PID
561
- stw r11, 8(r0)
562
- stw r12, 12(r0)
563
-#else
564336 mtspr SPRN_SPRG_SCRATCH3, r12
565337 mtspr SPRN_SPRG_SCRATCH4, r9
566
- mfcr r11
567
- mfspr r12, SPRN_PID
568
- mtspr SPRN_SPRG_SCRATCH6, r11
569
- mtspr SPRN_SPRG_SCRATCH5, r12
570
-#endif
338
+ mfcr r12
339
+ mfspr r9, SPRN_PID
340
+ mtspr SPRN_SPRG_SCRATCH5, r9
571341 mfspr r10, SPRN_SRR0 /* Get faulting address */
572342
573343 /* If we are faulting a kernel address, we have to use the
....@@ -590,28 +360,30 @@
590360 4:
591361 tophys(r11, r11)
592362 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
593
- lwz r12, 0(r11) /* Get L1 entry */
594
- andi. r9, r12, _PMD_PRESENT /* Check if it points to a PTE page */
363
+ lwz r11, 0(r11) /* Get L1 entry */
364
+ andi. r9, r11, _PMD_PRESENT /* Check if it points to a PTE page */
595365 beq 2f /* Bail if no table */
596366
597
- rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
598
- lwz r11, 0(r12) /* Get Linux PTE */
599
- andi. r9, r11, _PAGE_PRESENT
600
- beq 5f
367
+ rlwimi r11, r10, 22, 20, 29 /* Compute PTE address */
368
+ lwz r11, 0(r11) /* Get Linux PTE */
369
+ li r9, _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
370
+ andc. r9, r9, r11 /* Check permission */
371
+ bne 5f
601372
602
- ori r11, r11, _PAGE_ACCESSED
603
- stw r11, 0(r12)
373
+ rlwinm r9, r11, 1, _PAGE_RW /* dirty => rw */
374
+ and r9, r9, r11 /* hwwrite = dirty & rw */
375
+ rlwimi r11, r9, 0, _PAGE_RW /* replace rw by hwwrite */
604376
605377 /* Create TLB tag. This is the faulting address plus a static
606378 * set of bits. These are size, valid, E, U0.
607379 */
608
- li r12, 0x00c0
609
- rlwimi r10, r12, 0, 20, 31
380
+ li r9, 0x00c0
381
+ rlwimi r10, r9, 0, 20, 31
610382
611383 b finish_tlb_load
612384
613385 2: /* Check for possible large-page pmd entry */
614
- rlwinm. r9, r12, 2, 22, 24
386
+ rlwinm. r9, r11, 2, 22, 24
615387 beq 5f
616388
617389 /* Create TLB tag. This is the faulting address, plus a static
....@@ -619,7 +391,6 @@
619391 */
620392 ori r9, r9, 0x40
621393 rlwimi r10, r9, 0, 20, 31
622
- mr r11, r12
623394
624395 b finish_tlb_load
625396
....@@ -627,44 +398,28 @@
627398 /* The bailout. Restore registers to pre-exception conditions
628399 * and call the heavyweights to help us out.
629400 */
630
-#ifdef CONFIG_403GCX
631
- lwz r12, 12(r0)
632
- lwz r11, 8(r0)
633
- mtspr SPRN_PID, r12
634
- mtcr r11
635
- lwz r9, 4(r0)
636
- lwz r12, 0(r0)
637
-#else
638
- mfspr r12, SPRN_SPRG_SCRATCH5
639
- mfspr r11, SPRN_SPRG_SCRATCH6
640
- mtspr SPRN_PID, r12
641
- mtcr r11
401
+ mfspr r9, SPRN_SPRG_SCRATCH5
402
+ mtspr SPRN_PID, r9
403
+ mtcr r12
642404 mfspr r9, SPRN_SPRG_SCRATCH4
643405 mfspr r12, SPRN_SPRG_SCRATCH3
644
-#endif
645406 mfspr r11, SPRN_SPRG_SCRATCH1
646407 mfspr r10, SPRN_SPRG_SCRATCH0
647408 b InstructionAccess
648409
649
- EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE)
650
- EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE)
651
- EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
652
- EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
653
-#ifdef CONFIG_IBM405_ERR51
654
- /* 405GP errata 51 */
655
- START_EXCEPTION(0x1700, Trap_17)
656
- b DTLBMiss
657
-#else
658
- EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
659
-#endif
660
- EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
661
- EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
662
- EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE)
663
- EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE)
664
- EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE)
665
- EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE)
666
- EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE)
667
- EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE)
410
+ EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_STD)
411
+ EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_STD)
412
+ EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
413
+ EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_STD)
414
+ EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_STD)
415
+ EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
416
+ EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
417
+ EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_STD)
418
+ EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_STD)
419
+ EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_STD)
420
+ EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_STD)
421
+ EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_STD)
422
+ EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_STD)
668423
669424 /* Check for a single step debug exception while in an exception
670425 * handler before state has been saved. This is to catch the case
....@@ -717,7 +472,6 @@
717472 lwz r12,GPR12(r11)
718473 lwz r10,crit_r10@l(0)
719474 lwz r11,crit_r11@l(0)
720
- PPC405_ERR77_SYNC
721475 rfci
722476 b .
723477
....@@ -726,11 +480,11 @@
726480 addi r3,r1,STACK_FRAME_OVERHEAD
727481 EXC_XFER_TEMPLATE(DebugException, 0x2002, \
728482 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
729
- NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
483
+ crit_transfer_to_handler, ret_from_crit_exc)
730484
731485 /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
732486 Decrementer:
733
- NORMAL_EXCEPTION_PROLOG
487
+ EXCEPTION_PROLOG
734488 lis r0,TSR_PIS@h
735489 mtspr SPRN_TSR,r0 /* Clear the PIT exception */
736490 addi r3,r1,STACK_FRAME_OVERHEAD
....@@ -738,9 +492,9 @@
738492
739493 /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
740494 FITException:
741
- NORMAL_EXCEPTION_PROLOG
495
+ EXCEPTION_PROLOG
742496 addi r3,r1,STACK_FRAME_OVERHEAD;
743
- EXC_XFER_EE(0x1010, unknown_exception)
497
+ EXC_XFER_STD(0x1010, unknown_exception)
744498
745499 /* Watchdog Timer (WDT) Exception. (from 0x1020) */
746500 WDTException:
....@@ -748,19 +502,7 @@
748502 addi r3,r1,STACK_FRAME_OVERHEAD;
749503 EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2,
750504 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)),
751
- NOCOPY, crit_transfer_to_handler,
752
- ret_from_crit_exc)
753
-
754
-/*
755
- * The other Data TLB exceptions bail out to this point
756
- * if they can't resolve the lightweight TLB fault.
757
- */
758
-DataAccess:
759
- NORMAL_EXCEPTION_PROLOG
760
- mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
761
- stw r5,_ESR(r11)
762
- mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
763
- EXC_XFER_LITE(0x300, handle_page_fault)
505
+ crit_transfer_to_handler, ret_from_crit_exc)
764506
765507 /* Other PowerPC processors, namely those derived from the 6xx-series
766508 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
....@@ -773,7 +515,7 @@
773515 * miss get to this point to load the TLB.
774516 * r10 - TLB_TAG value
775517 * r11 - Linux PTE
776
- * r12, r9 - available to use
518
+ * r9 - available to use
777519 * PID - loaded with proper value when we get here
778520 * Upon exit, we reload everything and RFI.
779521 * Actually, it will fit now, but oh well.....a common place
....@@ -782,45 +524,32 @@
782524 tlb_4xx_index:
783525 .long 0
784526 finish_tlb_load:
785
- /* load the next available TLB index.
786
- */
787
- lwz r9, tlb_4xx_index@l(0)
788
- addi r9, r9, 1
789
- andi. r9, r9, (PPC40X_TLB_SIZE-1)
790
- stw r9, tlb_4xx_index@l(0)
791
-
792
-6:
793527 /*
794528 * Clear out the software-only bits in the PTE to generate the
795529 * TLB_DATA value. These are the bottom 2 bits of the RPM, the
796530 * top 3 bits of the zone field, and M.
797531 */
798
- li r12, 0x0ce2
799
- andc r11, r11, r12
532
+ li r9, 0x0ce2
533
+ andc r11, r11, r9
534
+
535
+ /* load the next available TLB index. */
536
+ lwz r9, tlb_4xx_index@l(0)
537
+ addi r9, r9, 1
538
+ andi. r9, r9, PPC40X_TLB_SIZE - 1
539
+ stw r9, tlb_4xx_index@l(0)
800540
801541 tlbwe r11, r9, TLB_DATA /* Load TLB LO */
802542 tlbwe r10, r9, TLB_TAG /* Load TLB HI */
803543
804544 /* Done...restore registers and get out of here.
805545 */
806
-#ifdef CONFIG_403GCX
807
- lwz r12, 12(r0)
808
- lwz r11, 8(r0)
809
- mtspr SPRN_PID, r12
810
- mtcr r11
811
- lwz r9, 4(r0)
812
- lwz r12, 0(r0)
813
-#else
814
- mfspr r12, SPRN_SPRG_SCRATCH5
815
- mfspr r11, SPRN_SPRG_SCRATCH6
816
- mtspr SPRN_PID, r12
817
- mtcr r11
546
+ mfspr r9, SPRN_SPRG_SCRATCH5
547
+ mtspr SPRN_PID, r9
548
+ mtcr r12
818549 mfspr r9, SPRN_SPRG_SCRATCH4
819550 mfspr r12, SPRN_SPRG_SCRATCH3
820
-#endif
821551 mfspr r11, SPRN_SPRG_SCRATCH1
822552 mfspr r10, SPRN_SPRG_SCRATCH0
823
- PPC405_ERR77_SYNC
824553 rfi /* Should sync shadow TLBs */
825554 b . /* prevent prefetch past rfi */
826555
....@@ -848,6 +577,9 @@
848577 /*
849578 * Decide what sort of machine this is and initialize the MMU.
850579 */
580
+#ifdef CONFIG_KASAN
581
+ bl kasan_early_init
582
+#endif
851583 li r3,0
852584 mr r4,r31
853585 bl machine_init
....@@ -880,7 +612,7 @@
880612 ori r6, r6, swapper_pg_dir@l
881613 lis r5, abatron_pteptrs@h
882614 ori r5, r5, abatron_pteptrs@l
883
- stw r5, 0xf0(r0) /* Must match your Abatron config file */
615
+ stw r5, 0xf0(0) /* Must match your Abatron config file */
884616 tophys(r5,r5)
885617 stw r6, 0(r5)
886618
....@@ -895,7 +627,7 @@
895627 b . /* prevent prefetch past rfi */
896628
897629 /* Set up the initial MMU state so we can do the first level of
898
- * kernel initialization. This maps the first 16 MBytes of memory 1:1
630
+ * kernel initialization. This maps the first 32 MBytes of memory 1:1
899631 * virtual to physical and more importantly sets the cache mode.
900632 */
901633 initial_mmu:
....@@ -932,6 +664,12 @@
932664 tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */
933665 tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
934666
667
+ li r0,62 /* TLB slot 62 */
668
+ addis r4,r4,SZ_16M@h
669
+ addis r3,r3,SZ_16M@h
670
+ tlbwe r4,r0,TLB_DATA /* Load the data portion of the entry */
671
+ tlbwe r3,r0,TLB_TAG /* Load the tag portion of the entry */
672
+
935673 isync
936674
937675 /* Establish the exception vector base
....@@ -953,9 +691,8 @@
953691 /* Context switch the PTE pointer for the Abatron BDI2000.
954692 * The PGDIR is the second parameter.
955693 */
956
- lis r5, KERNELBASE@h
957
- lwz r5, 0xf0(r5)
958
- stw r4, 0x4(r5)
694
+ lis r5, abatron_pteptrs@ha
695
+ stw r4, abatron_pteptrs@l + 0x4(r5)
959696 #endif
960697 sync
961698 mtspr SPRN_PID,r3