hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/powerpc/include/asm/nohash/32/pte-fsl-booke.h
....@@ -31,11 +31,44 @@
3131 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
3232 #define _PAGE_SPECIAL 0x00800 /* S: Special page */
3333
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+#define _PAGE_KERNEL_RO 0
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+#define _PAGE_KERNEL_ROX _PAGE_EXEC
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+#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW)
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+#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
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+
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+/* No page size encoding in the linux PTE */
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+#define _PAGE_PSIZE 0
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+
3442 #define _PMD_PRESENT 0
3543 #define _PMD_PRESENT_MASK (PAGE_MASK)
3644 #define _PMD_BAD (~PAGE_MASK)
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+#define _PMD_USER 0
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+
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+#define _PTE_NONE_MASK 0
3748
3849 #define PTE_WIMGE_SHIFT (6)
3950
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+/*
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+ * We define 2 sets of base prot bits, one for basic pages (ie,
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+ * cacheable kernel and user pages) and one for non cacheable
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+ * pages. We always set _PAGE_COHERENT when SMP is enabled or
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+ * the processor might need it for DMA coherency.
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+ */
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+#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
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+#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
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+#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
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+#else
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+#define _PAGE_BASE (_PAGE_BASE_NC)
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+#endif
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+
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+/* Permission masks used to generate the __P and __S table */
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+#define PAGE_NONE __pgprot(_PAGE_BASE)
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+#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
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+#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
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+#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
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+#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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+#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
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+#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
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+
4073 #endif /* __KERNEL__ */
4174 #endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */