add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/powerpc/include/asm/nohash/32/pte-8xx.h
..
..
@@ -29,35 +29,112 @@
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  */
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 /* Definitions for 8xx embedded chips. */
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-#define _PAGE_PRESENT	0x0001	/* Page is valid */
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-#define _PAGE_NO_CACHE	0x0002	/* I: cache inhibit */
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-#define _PAGE_PRIVILEGED	0x0004	/* No ASID (context) compare */
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-#define _PAGE_HUGE	0x0008	/* SPS: Small Page Size (1 if 16k, 512k or 8M)*/
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+#define _PAGE_PRESENT	0x0001	/* V: Page is valid */
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+#define _PAGE_NO_CACHE	0x0002	/* CI: cache inhibit */
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+#define _PAGE_SH	0x0004	/* SH: No ASID (context) compare */
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+#define _PAGE_SPS	0x0008	/* SPS: Small Page Size (1 if 16k, 512k or 8M)*/
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 #define _PAGE_DIRTY	0x0100	/* C: page changed */
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 /* These 4 software bits must be masked out when the L2 entry is loaded
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  * into the TLB.
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  */
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 #define _PAGE_GUARDED	0x0010	/* Copied to L1 G entry in DTLB */
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-#define _PAGE_SPECIAL	0x0020	/* SW entry */
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+#define _PAGE_ACCESSED	0x0020	/* Copied to L1 APG 1 entry in I/DTLB */
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 #define _PAGE_EXEC	0x0040	/* Copied to PP (bit 21) in ITLB */
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-#define _PAGE_ACCESSED	0x0080	/* software: page referenced */
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+#define _PAGE_SPECIAL	0x0080	/* SW entry */
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 #define _PAGE_NA	0x0200	/* Supervisor NA, User no access */
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 #define _PAGE_RO	0x0600	/* Supervisor RO, User no access */
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+#define _PAGE_HUGE	0x0800	/* Copied to L1 PS bit 29 */
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+
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+/* cache related flags non existing on 8xx */
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+#define _PAGE_COHERENT	0
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+#define _PAGE_WRITETHRU	0
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+
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+#define _PAGE_KERNEL_RO		(_PAGE_SH | _PAGE_RO)
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+#define _PAGE_KERNEL_ROX	(_PAGE_SH | _PAGE_RO | _PAGE_EXEC)
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+#define _PAGE_KERNEL_RW		(_PAGE_SH | _PAGE_DIRTY)
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+#define _PAGE_KERNEL_RWX	(_PAGE_SH | _PAGE_DIRTY | _PAGE_EXEC)
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+
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 #define _PMD_PRESENT	0x0001
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-#define _PMD_BAD	0x0fd0
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+#define _PMD_PRESENT_MASK	_PMD_PRESENT
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+#define _PMD_BAD	0x0f90
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 #define _PMD_PAGE_MASK	0x000c
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 #define _PMD_PAGE_8M	0x000c
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 #define _PMD_PAGE_512K	0x0004
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-#define _PMD_USER	0x0020	/* APG 1 */
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+#define _PMD_ACCESSED	0x0020	/* APG 1 */
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+#define _PMD_USER	0x0040	/* APG 2 */
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-/* Until my rework is finished, 8xx still needs atomic PTE updates */
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-#define PTE_ATOMIC_UPDATES	1
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+#define _PTE_NONE_MASK	0
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 #ifdef CONFIG_PPC_16K_PAGES
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-#define _PAGE_PSIZE	_PAGE_HUGE
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+#define _PAGE_PSIZE	_PAGE_SPS
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+#else
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+#define _PAGE_PSIZE		0
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+#endif
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+
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+#define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
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+#define _PAGE_BASE	(_PAGE_BASE_NC)
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+
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+/* Permission masks used to generate the __P and __S table */
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+#define PAGE_NONE	__pgprot(_PAGE_BASE | _PAGE_NA)
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+#define PAGE_SHARED	__pgprot(_PAGE_BASE)
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+#define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_EXEC)
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+#define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_RO)
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+#define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_RO | _PAGE_EXEC)
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+#define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_RO)
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+#define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_RO | _PAGE_EXEC)
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+
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+#ifndef __ASSEMBLY__
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+static inline pte_t pte_wrprotect(pte_t pte)
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+{
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+	return __pte(pte_val(pte) | _PAGE_RO);
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+}
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+
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+#define pte_wrprotect pte_wrprotect
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+
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+static inline int pte_write(pte_t pte)
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+{
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+	return !(pte_val(pte) & _PAGE_RO);
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+}
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+
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+#define pte_write pte_write
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+
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+static inline pte_t pte_mkwrite(pte_t pte)
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+{
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+	return __pte(pte_val(pte) & ~_PAGE_RO);
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+}
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+
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+#define pte_mkwrite pte_mkwrite
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+
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+static inline bool pte_user(pte_t pte)
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+{
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+	return !(pte_val(pte) & _PAGE_SH);
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+}
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+
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+#define pte_user pte_user
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+
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+static inline pte_t pte_mkprivileged(pte_t pte)
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+{
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+	return __pte(pte_val(pte) | _PAGE_SH);
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+}
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+
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+#define pte_mkprivileged pte_mkprivileged
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+
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+static inline pte_t pte_mkuser(pte_t pte)
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+{
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+	return __pte(pte_val(pte) & ~_PAGE_SH);
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+}
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+
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+#define pte_mkuser pte_mkuser
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+
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+static inline pte_t pte_mkhuge(pte_t pte)
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+{
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+	return __pte(pte_val(pte) | _PAGE_SPS | _PAGE_HUGE);
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+}
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+
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+#define pte_mkhuge pte_mkhuge
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 #endif
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 #endif /* __KERNEL__ */