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1 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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2 | 2 | #ifndef _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ |
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3 | 3 | #define _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_ |
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| 4 | + |
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4 | 5 | /* |
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5 | 6 | * 32-bit hash table MMU support |
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6 | 7 | */ |
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.. | .. |
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34 | 35 | #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \ |
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35 | 36 | ((x & 0x0000000e00000000ULL) >> 24) | \ |
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36 | 37 | ((x & 0x0000000100000000ULL) >> 30))) |
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| 38 | +#define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \ |
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| 39 | + (((u64)(x) << 24) & 0x0000000e00000000ULL) | \ |
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| 40 | + (((u64)(x) << 30) & 0x0000000100000000ULL)) |
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37 | 41 | #else |
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38 | 42 | #define BAT_PHYS_ADDR(x) (x) |
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| 43 | +#define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000) |
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39 | 44 | #endif |
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40 | 45 | |
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41 | 46 | struct ppc_bat { |
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.. | .. |
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53 | 58 | #define PP_RWRX 1 /* Supervisor read/write, User read */ |
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54 | 59 | #define PP_RWRW 2 /* Supervisor read/write, User read/write */ |
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55 | 60 | #define PP_RXRX 3 /* Supervisor read, User read */ |
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| 61 | + |
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| 62 | +/* Values for Segment Registers */ |
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| 63 | +#define SR_NX 0x10000000 /* No Execute */ |
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| 64 | +#define SR_KP 0x20000000 /* User key */ |
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| 65 | +#define SR_KS 0x40000000 /* Supervisor key */ |
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56 | 66 | |
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57 | 67 | #ifndef __ASSEMBLY__ |
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58 | 68 | |
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.. | .. |
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83 | 93 | unsigned long vdso_base; |
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84 | 94 | } mm_context_t; |
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85 | 95 | |
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| 96 | +void update_bats(void); |
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| 97 | +static inline void cleanup_cpu_mmu_context(void) { }; |
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| 98 | + |
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| 99 | +/* patch sites */ |
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| 100 | +extern s32 patch__hash_page_A0, patch__hash_page_A1, patch__hash_page_A2; |
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| 101 | +extern s32 patch__hash_page_B, patch__hash_page_C; |
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| 102 | +extern s32 patch__flush_hash_A0, patch__flush_hash_A1, patch__flush_hash_A2; |
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| 103 | +extern s32 patch__flush_hash_B; |
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| 104 | + |
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| 105 | +int __init find_free_bat(void); |
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| 106 | +unsigned int bat_block_size(unsigned long base, unsigned long top); |
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86 | 107 | #endif /* !__ASSEMBLY__ */ |
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87 | 108 | |
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88 | 109 | /* We happily ignore the smaller BATs on 601, we don't actually use |
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