add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/parisc/kernel/inventory.c
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@@ -1,10 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * inventory.c
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- *
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- * This program is free software; you can redistribute it and/or
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- * modify it under the terms of the GNU General Public License
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- * as published by the Free Software Foundation; either version
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- * 2 of the License, or (at your option) any later version.
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  *
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  * Copyright (c) 1999 The Puffin Group (David Kennedy and Alex deVries)
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  * Copyright (c) 2001 Matthew Wilcox for Hewlett-Packard
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@@ -23,6 +19,7 @@
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 #include <linux/init.h>
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 #include <linux/slab.h>
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 #include <linux/mm.h>
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+#include <linux/platform_device.h>
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 #include <asm/hardware.h>
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 #include <asm/io.h>
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 #include <asm/mmzone.h>
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@@ -31,6 +28,7 @@
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 #include <asm/processor.h>
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 #include <asm/page.h>
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 #include <asm/parisc-device.h>
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+#include <asm/tlbflush.h>
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32
 
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 /*
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 ** Debug options
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@@ -38,11 +36,12 @@
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 */
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 #undef DEBUG_PAT
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38
 
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-int pdc_type __read_mostly = PDC_TYPE_ILLEGAL;
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+int pdc_type __ro_after_init = PDC_TYPE_ILLEGAL;
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40
 
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 /* cell number and location (PAT firmware only) */
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-unsigned long parisc_cell_num __read_mostly;
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-unsigned long parisc_cell_loc __read_mostly;
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+unsigned long parisc_cell_num __ro_after_init;
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+unsigned long parisc_cell_loc __ro_after_init;
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+unsigned long parisc_pat_pdc_cap __ro_after_init;
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45
 
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 void __init setup_pdc(void)
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@@ -81,12 +80,21 @@
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 #ifdef CONFIG_64BIT
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 	status = pdc_pat_cell_get_number(&cell_info);
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 	if (status == PDC_OK) {
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+		unsigned long legacy_rev, pat_rev;
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 		pdc_type = PDC_TYPE_PAT;
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 		pr_cont("64 bit PAT.\n");
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 		parisc_cell_num = cell_info.cell_num;
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 		parisc_cell_loc = cell_info.cell_loc;
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 		pr_info("PAT: Running on cell %lu and location %lu.\n",
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 			parisc_cell_num, parisc_cell_loc);
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+		status = pdc_pat_pd_get_pdc_revisions(&legacy_rev,
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+			&pat_rev, &parisc_pat_pdc_cap);
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+		pr_info("PAT: legacy revision 0x%lx, pat_rev 0x%lx, pdc_cap 0x%lx, S-PTLB %d, HPMC_RENDEZ %d.\n",
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+			legacy_rev, pat_rev, parisc_pat_pdc_cap,
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+			parisc_pat_pdc_cap
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+			 & PDC_PAT_CAPABILITY_BIT_SIMULTANEOUS_PTLB ? 1:0,
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+			parisc_pat_pdc_cap
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+			 & PDC_PAT_CAPABILITY_BIT_PDC_HPMC_RENDEZ   ? 1:0);
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 		return;
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 	}
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 #endif
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@@ -628,4 +636,39 @@
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 	}
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 	printk(KERN_INFO "Found devices:\n");
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 	print_parisc_devices();
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+
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+#if defined(CONFIG_64BIT) && defined(CONFIG_SMP)
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+	pa_serialize_tlb_flushes = machine_has_merced_bus();
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+	if (pa_serialize_tlb_flushes)
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+		pr_info("Merced bus found: Enable PxTLB serialization.\n");
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+#endif
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+
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+#if defined(CONFIG_FW_CFG_SYSFS)
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+	if (running_on_qemu) {
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+		struct resource res[3] = {0,};
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+		unsigned int base;
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+
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+		base = ((unsigned long long) PAGE0->pad0[2] << 32)
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+			| PAGE0->pad0[3]; /* SeaBIOS stored it here */
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+
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+		res[0].name = "fw_cfg";
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+		res[0].start = base;
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+		res[0].end = base + 8 - 1;
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+		res[0].flags = IORESOURCE_MEM;
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+
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+		res[1].name = "ctrl";
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+		res[1].start = 0;
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+		res[1].flags = IORESOURCE_REG;
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+
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+		res[2].name = "data";
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+		res[2].start = 4;
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+		res[2].flags = IORESOURCE_REG;
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+
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+		if (base) {
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+			pr_info("Found qemu fw_cfg interface at %#08x\n", base);
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+			platform_device_register_simple("fw_cfg",
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+				PLATFORM_DEVID_NONE, res, 3);
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+		}
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+	}
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+#endif
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 }