add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/nds32/Kconfig.cpu
..
..
@@ -1,3 +1,4 @@
1
+# SPDX-License-Identifier: GPL-2.0-only
1
2
 comment "Processor Features"
2
3
 
3
4
 config CPU_BIG_ENDIAN
..
..
@@ -6,6 +7,40 @@
6
7
 config CPU_LITTLE_ENDIAN
7
8
 	bool "Little endian"
8
9
 	default y
10
+
11
+config FPU
12
+	bool "FPU support"
13
+	default n
14
+	help
15
+	  If FPU ISA is used in user space, this configuration shall be Y to
16
+          enable required support in kernel such as fpu context switch and
17
+          fpu exception handler.
18
+
19
+	  If no FPU ISA is used in user space, say N.
20
+
21
+config LAZY_FPU
22
+	bool "lazy FPU support"
23
+	depends on FPU
24
+	default y
25
+	help
26
+	  Say Y here to enable the lazy FPU scheme. The lazy FPU scheme can
27
+          enhance system performance by reducing the context switch
28
+	  frequency of the FPU register.
29
+
30
+	  For normal case, say Y.
31
+
32
+config SUPPORT_DENORMAL_ARITHMETIC
33
+	bool "Denormal arithmetic support"
34
+	depends on FPU
35
+	default n
36
+	help
37
+	  Say Y here to enable arithmetic of denormalized number. Enabling
38
+	  this feature can enhance the precision for tininess number.
39
+	  However, performance loss in float point calculations is
40
+	  possibly significant due to additional FPU exception.
41
+
42
+	  If the calculated tolerance for tininess number is not critical,
43
+	  say N to prevent performance loss.
9
44
 
10
45
 config HWZOL
11
46
 	bool "hardware zero overhead loop support"
..
..
@@ -38,7 +73,7 @@
38
73
 	  the cache aliasing issue. The rest cpus(N13, N10 and D10) are
39
74
 	  implemented as VIPT data cache. It may cause the cache aliasing issue
40
75
 	  if its cache way size is larger than page size. You can specify the
41
-	  CPU type direcly or choose CPU_V3 if unsure.
76
+	  CPU type directly or choose CPU_V3 if unsure.
42
77
 
43
78
           A kernel built for N10 is able to run on N15, D15, N13, N10 or D10.
44
79
           A kernel built for N15 is able to run on N15 or D15.
..
..
@@ -122,6 +157,7 @@
122
157
 config HIGHMEM
123
158
 	bool "High Memory Support"
124
159
 	depends on MMU && !CPU_CACHE_ALIASING
160
+	select KMAP_LOCAL
125
161
 	help
126
162
 	  The address space of Andes processors is only 4 Gigabytes large
127
163
 	  and it has to accommodate user address space, kernel address
..
..
@@ -143,6 +179,13 @@
143
179
 	  Say Y here to enable L2 cache if your SoC are integrated with L2CC.
144
180
 	  If unsure, say N.
145
181
 
182
+config HW_PRE
183
+	bool "Enable hardware prefetcher"
184
+	default y
185
+	help
186
+	  Say Y here to enable hardware prefetcher feature.
187
+	  Only when CPU_VER.REV >= 0x09 can support.
188
+
146
189
 menu "Memory configuration"
147
190
 
148
191
 choice