add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/mips/mm/tlb-r4k.c
..
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@@ -21,7 +21,6 @@
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 #include <asm/bootinfo.h>
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 #include <asm/hazards.h>
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 #include <asm/mmu_context.h>
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-#include <asm/pgtable.h>
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 #include <asm/tlb.h>
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 #include <asm/tlbmisc.h>
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26
 
..
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@@ -35,10 +34,10 @@
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 static inline void flush_micro_tlb(void)
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 {
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 	switch (current_cpu_type()) {
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-	case CPU_LOONGSON2:
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+	case CPU_LOONGSON2EF:
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 		write_c0_diag(LOONGSON_DIAG_ITLB);
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 		break;
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-	case CPU_LOONGSON3:
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+	case CPU_LOONGSON64:
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 		write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB);
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 		break;
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 	default:
..
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@@ -104,23 +103,6 @@
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 }
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 EXPORT_SYMBOL(local_flush_tlb_all);
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105
 
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-/* All entries common to a mm share an asid.  To effectively flush
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-   these entries, we just bump the asid. */
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-void local_flush_tlb_mm(struct mm_struct *mm)
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-{
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-	int cpu;
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-
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-	preempt_disable();
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-
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-	cpu = smp_processor_id();
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-
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-	if (cpu_context(cpu, mm) != 0) {
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-		drop_mmu_context(mm, cpu);
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-	}
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-
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-	preempt_enable();
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-}
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-
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 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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 	unsigned long end)
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 {
..
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@@ -137,14 +119,23 @@
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 		if (size <= (current_cpu_data.tlbsizeftlbsets ?
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 			     current_cpu_data.tlbsize / 8 :
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 			     current_cpu_data.tlbsize / 2)) {
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-			int oldpid = read_c0_entryhi();
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+			unsigned long old_entryhi, old_mmid;
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 			int newpid = cpu_asid(cpu, mm);
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+
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+			old_entryhi = read_c0_entryhi();
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+			if (cpu_has_mmid) {
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+				old_mmid = read_c0_memorymapid();
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+				write_c0_memorymapid(newpid);
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+			}
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130
 
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 			htw_stop();
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 			while (start < end) {
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 				int idx;
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-				write_c0_entryhi(start | newpid);
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+				if (cpu_has_mmid)
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+					write_c0_entryhi(start);
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+				else
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+					write_c0_entryhi(start | newpid);
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 				start += (PAGE_SIZE << 1);
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 				mtc0_tlbw_hazard();
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 				tlb_probe();
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@@ -160,10 +151,12 @@
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 				tlb_write_indexed();
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 			}
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 			tlbw_use_hazard();
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-			write_c0_entryhi(oldpid);
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+			write_c0_entryhi(old_entryhi);
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+			if (cpu_has_mmid)
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+				write_c0_memorymapid(old_mmid);
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 			htw_start();
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 		} else {
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-			drop_mmu_context(mm, cpu);
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+			drop_mmu_context(mm);
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 		}
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 		flush_micro_tlb();
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 		local_irq_restore(flags);
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@@ -220,15 +213,21 @@
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 	int cpu = smp_processor_id();
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214
 
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 	if (cpu_context(cpu, vma->vm_mm) != 0) {
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-		unsigned long flags;
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-		int oldpid, newpid, idx;
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+		unsigned long old_mmid;
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+		unsigned long flags, old_entryhi;
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+		int idx;
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219
 
226
-		newpid = cpu_asid(cpu, vma->vm_mm);
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 		page &= (PAGE_MASK << 1);
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 		local_irq_save(flags);
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-		oldpid = read_c0_entryhi();
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+		old_entryhi = read_c0_entryhi();
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223
 		htw_stop();
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-		write_c0_entryhi(page | newpid);
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+		if (cpu_has_mmid) {
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+			old_mmid = read_c0_memorymapid();
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+			write_c0_entryhi(page);
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+			write_c0_memorymapid(cpu_asid(cpu, vma->vm_mm));
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+		} else {
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+			write_c0_entryhi(page | cpu_asid(cpu, vma->vm_mm));
230
+		}
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 		mtc0_tlbw_hazard();
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232
 		tlb_probe();
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233
 		tlb_probe_hazard();
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@@ -244,7 +243,9 @@
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 		tlbw_use_hazard();
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244
 
246
245
 	finish:
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-		write_c0_entryhi(oldpid);
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+		write_c0_entryhi(old_entryhi);
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+		if (cpu_has_mmid)
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+			write_c0_memorymapid(old_mmid);
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 		htw_start();
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 		flush_micro_tlb_vm(vma);
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 		local_irq_restore(flags);
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@@ -293,6 +294,7 @@
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 {
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 	unsigned long flags;
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 	pgd_t *pgdp;
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+	p4d_t *p4dp;
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 	pud_t *pudp;
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 	pmd_t *pmdp;
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 	pte_t *ptep;
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@@ -307,14 +309,19 @@
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 	local_irq_save(flags);
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310
 
309
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 	htw_stop();
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-	pid = read_c0_entryhi() & cpu_asid_mask(&current_cpu_data);
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 	address &= (PAGE_MASK << 1);
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-	write_c0_entryhi(address | pid);
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+	if (cpu_has_mmid) {
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+		write_c0_entryhi(address);
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+	} else {
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+		pid = read_c0_entryhi() & cpu_asid_mask(&current_cpu_data);
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+		write_c0_entryhi(address | pid);
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+	}
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 	pgdp = pgd_offset(vma->vm_mm, address);
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 	mtc0_tlbw_hazard();
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 	tlb_probe();
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 	tlb_probe_hazard();
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-	pudp = pud_offset(pgdp, address);
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+	p4dp = p4d_offset(pgdp, address);
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+	pudp = pud_offset(p4dp, address);
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 	pmdp = pmd_offset(pudp, address);
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 	idx = read_c0_index();
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 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
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@@ -375,12 +382,17 @@
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 #ifdef CONFIG_XPA
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 	panic("Broken for XPA kernels");
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 #else
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+	unsigned int old_mmid;
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386
 	unsigned long flags;
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 	unsigned long wired;
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 	unsigned long old_pagemask;
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 	unsigned long old_ctx;
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390
 
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 	local_irq_save(flags);
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+	if (cpu_has_mmid) {
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+		old_mmid = read_c0_memorymapid();
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+		write_c0_memorymapid(MMID_KERNEL_WIRED);
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+	}
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 	/* Save old context and create impossible VPN2 value */
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 	old_ctx = read_c0_entryhi();
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398
 	htw_stop();
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@@ -398,6 +410,8 @@
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 	tlbw_use_hazard();
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400
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 	write_c0_entryhi(old_ctx);
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+	if (cpu_has_mmid)
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+		write_c0_memorymapid(old_mmid);
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 	tlbw_use_hazard();	/* What is the hazard here? */
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 	htw_start();
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 	write_c0_pagemask(old_pagemask);