hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/mips/mm/tlb-r4k.c
....@@ -21,7 +21,6 @@
2121 #include <asm/bootinfo.h>
2222 #include <asm/hazards.h>
2323 #include <asm/mmu_context.h>
24
-#include <asm/pgtable.h>
2524 #include <asm/tlb.h>
2625 #include <asm/tlbmisc.h>
2726
....@@ -35,10 +34,10 @@
3534 static inline void flush_micro_tlb(void)
3635 {
3736 switch (current_cpu_type()) {
38
- case CPU_LOONGSON2:
37
+ case CPU_LOONGSON2EF:
3938 write_c0_diag(LOONGSON_DIAG_ITLB);
4039 break;
41
- case CPU_LOONGSON3:
40
+ case CPU_LOONGSON64:
4241 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB);
4342 break;
4443 default:
....@@ -104,23 +103,6 @@
104103 }
105104 EXPORT_SYMBOL(local_flush_tlb_all);
106105
107
-/* All entries common to a mm share an asid. To effectively flush
108
- these entries, we just bump the asid. */
109
-void local_flush_tlb_mm(struct mm_struct *mm)
110
-{
111
- int cpu;
112
-
113
- preempt_disable();
114
-
115
- cpu = smp_processor_id();
116
-
117
- if (cpu_context(cpu, mm) != 0) {
118
- drop_mmu_context(mm, cpu);
119
- }
120
-
121
- preempt_enable();
122
-}
123
-
124106 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
125107 unsigned long end)
126108 {
....@@ -137,14 +119,23 @@
137119 if (size <= (current_cpu_data.tlbsizeftlbsets ?
138120 current_cpu_data.tlbsize / 8 :
139121 current_cpu_data.tlbsize / 2)) {
140
- int oldpid = read_c0_entryhi();
122
+ unsigned long old_entryhi, old_mmid;
141123 int newpid = cpu_asid(cpu, mm);
124
+
125
+ old_entryhi = read_c0_entryhi();
126
+ if (cpu_has_mmid) {
127
+ old_mmid = read_c0_memorymapid();
128
+ write_c0_memorymapid(newpid);
129
+ }
142130
143131 htw_stop();
144132 while (start < end) {
145133 int idx;
146134
147
- write_c0_entryhi(start | newpid);
135
+ if (cpu_has_mmid)
136
+ write_c0_entryhi(start);
137
+ else
138
+ write_c0_entryhi(start | newpid);
148139 start += (PAGE_SIZE << 1);
149140 mtc0_tlbw_hazard();
150141 tlb_probe();
....@@ -160,10 +151,12 @@
160151 tlb_write_indexed();
161152 }
162153 tlbw_use_hazard();
163
- write_c0_entryhi(oldpid);
154
+ write_c0_entryhi(old_entryhi);
155
+ if (cpu_has_mmid)
156
+ write_c0_memorymapid(old_mmid);
164157 htw_start();
165158 } else {
166
- drop_mmu_context(mm, cpu);
159
+ drop_mmu_context(mm);
167160 }
168161 flush_micro_tlb();
169162 local_irq_restore(flags);
....@@ -220,15 +213,21 @@
220213 int cpu = smp_processor_id();
221214
222215 if (cpu_context(cpu, vma->vm_mm) != 0) {
223
- unsigned long flags;
224
- int oldpid, newpid, idx;
216
+ unsigned long old_mmid;
217
+ unsigned long flags, old_entryhi;
218
+ int idx;
225219
226
- newpid = cpu_asid(cpu, vma->vm_mm);
227220 page &= (PAGE_MASK << 1);
228221 local_irq_save(flags);
229
- oldpid = read_c0_entryhi();
222
+ old_entryhi = read_c0_entryhi();
230223 htw_stop();
231
- write_c0_entryhi(page | newpid);
224
+ if (cpu_has_mmid) {
225
+ old_mmid = read_c0_memorymapid();
226
+ write_c0_entryhi(page);
227
+ write_c0_memorymapid(cpu_asid(cpu, vma->vm_mm));
228
+ } else {
229
+ write_c0_entryhi(page | cpu_asid(cpu, vma->vm_mm));
230
+ }
232231 mtc0_tlbw_hazard();
233232 tlb_probe();
234233 tlb_probe_hazard();
....@@ -244,7 +243,9 @@
244243 tlbw_use_hazard();
245244
246245 finish:
247
- write_c0_entryhi(oldpid);
246
+ write_c0_entryhi(old_entryhi);
247
+ if (cpu_has_mmid)
248
+ write_c0_memorymapid(old_mmid);
248249 htw_start();
249250 flush_micro_tlb_vm(vma);
250251 local_irq_restore(flags);
....@@ -293,6 +294,7 @@
293294 {
294295 unsigned long flags;
295296 pgd_t *pgdp;
297
+ p4d_t *p4dp;
296298 pud_t *pudp;
297299 pmd_t *pmdp;
298300 pte_t *ptep;
....@@ -307,14 +309,19 @@
307309 local_irq_save(flags);
308310
309311 htw_stop();
310
- pid = read_c0_entryhi() & cpu_asid_mask(&current_cpu_data);
311312 address &= (PAGE_MASK << 1);
312
- write_c0_entryhi(address | pid);
313
+ if (cpu_has_mmid) {
314
+ write_c0_entryhi(address);
315
+ } else {
316
+ pid = read_c0_entryhi() & cpu_asid_mask(&current_cpu_data);
317
+ write_c0_entryhi(address | pid);
318
+ }
313319 pgdp = pgd_offset(vma->vm_mm, address);
314320 mtc0_tlbw_hazard();
315321 tlb_probe();
316322 tlb_probe_hazard();
317
- pudp = pud_offset(pgdp, address);
323
+ p4dp = p4d_offset(pgdp, address);
324
+ pudp = pud_offset(p4dp, address);
318325 pmdp = pmd_offset(pudp, address);
319326 idx = read_c0_index();
320327 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
....@@ -375,12 +382,17 @@
375382 #ifdef CONFIG_XPA
376383 panic("Broken for XPA kernels");
377384 #else
385
+ unsigned int old_mmid;
378386 unsigned long flags;
379387 unsigned long wired;
380388 unsigned long old_pagemask;
381389 unsigned long old_ctx;
382390
383391 local_irq_save(flags);
392
+ if (cpu_has_mmid) {
393
+ old_mmid = read_c0_memorymapid();
394
+ write_c0_memorymapid(MMID_KERNEL_WIRED);
395
+ }
384396 /* Save old context and create impossible VPN2 value */
385397 old_ctx = read_c0_entryhi();
386398 htw_stop();
....@@ -398,6 +410,8 @@
398410 tlbw_use_hazard();
399411
400412 write_c0_entryhi(old_ctx);
413
+ if (cpu_has_mmid)
414
+ write_c0_memorymapid(old_mmid);
401415 tlbw_use_hazard(); /* What is the hazard here? */
402416 htw_start();
403417 write_c0_pagemask(old_pagemask);