add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/mips/boot/dts/ingenic/jz4780.dtsi
..
..
@@ -1,11 +1,35 @@
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 // SPDX-License-Identifier: GPL-2.0
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 #include <dt-bindings/clock/jz4780-cgu.h>
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+#include <dt-bindings/clock/ingenic,tcu.h>
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 #include <dt-bindings/dma/jz4780-dma.h>
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5
 
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 / {
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 	#address-cells = <1>;
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 	#size-cells = <1>;
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 	compatible = "ingenic,jz4780";
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+
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+	cpus {
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+		#address-cells = <1>;
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+		#size-cells = <0>;
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+
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+		cpu0: cpu@0 {
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+			device_type = "cpu";
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+			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
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+			reg = <0>;
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+
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+			clocks = <&cgu JZ4780_CLK_CPU>;
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+			clock-names = "cpu";
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+		};
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+
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+		cpu1: cpu@1 {
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+			device_type = "cpu";
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+			compatible = "ingenic,xburst-fpu1.0-mxu1.1";
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+			reg = <1>;
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+
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+			clocks = <&cgu JZ4780_CLK_CORE1>;
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+			clock-names = "cpu";
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+		};
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+	};
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 	cpuintc: interrupt-controller {
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 		#address-cells = <0>;
..
..
@@ -44,6 +68,61 @@
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 		clock-names = "ext", "rtc";
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 		#clock-cells = <1>;
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+	};
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+
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+	tcu: timer@10002000 {
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+		compatible = "ingenic,jz4780-tcu",
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+			     "ingenic,jz4770-tcu",
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+			     "simple-mfd";
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+		reg = <0x10002000 0x1000>;
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+		#address-cells = <1>;
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+		#size-cells = <1>;
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+		ranges = <0x0 0x10002000 0x1000>;
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+
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+		#clock-cells = <1>;
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+
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+		clocks = <&cgu JZ4780_CLK_RTCLK>,
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+			 <&cgu JZ4780_CLK_EXCLK>,
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+			 <&cgu JZ4780_CLK_PCLK>;
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+		clock-names = "rtc", "ext", "pclk";
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+
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+		interrupt-controller;
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+		#interrupt-cells = <1>;
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+
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+		interrupt-parent = <&intc>;
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+		interrupts = <27 26 25>;
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+
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+		watchdog: watchdog@0 {
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+			compatible = "ingenic,jz4780-watchdog";
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+			reg = <0x0 0xc>;
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+
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+			clocks = <&tcu TCU_CLK_WDT>;
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+			clock-names = "wdt";
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+		};
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+
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+		pwm: pwm@40 {
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+			compatible = "ingenic,jz4780-pwm", "ingenic,jz4740-pwm";
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+			reg = <0x40 0x80>;
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+
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+			#pwm-cells = <3>;
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+
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+			clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
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+				 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
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+				 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
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+				 <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
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+			clock-names = "timer0", "timer1", "timer2", "timer3",
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+				      "timer4", "timer5", "timer6", "timer7";
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+		};
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+
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+		ost: timer@e0 {
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+			compatible = "ingenic,jz4780-ost", "ingenic,jz4770-ost";
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+			reg = <0xe0 0x20>;
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+
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+			clocks = <&tcu TCU_CLK_OST>;
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+			clock-names = "ost";
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+
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+			interrupts = <15>;
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+		};
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 	};
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127
 
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 	rtc_dev: rtc@10003000 {
..
..
@@ -164,8 +243,7 @@
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 		gpio-miso = <&gpe 14 0>;
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 		gpio-sck = <&gpe 15 0>;
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 		gpio-mosi = <&gpe 17 0>;
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-		cs-gpios = <&gpe 16 0
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-			    &gpe 18 0>;
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+		cs-gpios = <&gpe 16 0>, <&gpe 18 0>;
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 		spidev@0 {
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 			compatible = "spidev";
..
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@@ -239,34 +317,127 @@
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 		status = "disabled";
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 	};
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-	watchdog: watchdog@10002000 {
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-		compatible = "ingenic,jz4780-watchdog";
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-		reg = <0x10002000 0x10>;
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+	i2c0: i2c@10050000 {
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+		compatible = "ingenic,jz4780-i2c";
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+		#address-cells = <1>;
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+		#size-cells = <0>;
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-		clocks = <&cgu JZ4780_CLK_RTCLK>;
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-		clock-names = "rtc";
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-	};
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+		reg = <0x10050000 0x1000>;
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-	nemc: nemc@13410000 {
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-		compatible = "ingenic,jz4780-nemc";
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-		reg = <0x13410000 0x10000>;
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-		#address-cells = <2>;
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-		#size-cells = <1>;
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-		ranges = <1 0 0x1b000000 0x1000000
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-			  2 0 0x1a000000 0x1000000
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-			  3 0 0x19000000 0x1000000
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-			  4 0 0x18000000 0x1000000
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-			  5 0 0x17000000 0x1000000
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-			  6 0 0x16000000 0x1000000>;
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+		interrupt-parent = <&intc>;
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+		interrupts = <60>;
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-		clocks = <&cgu JZ4780_CLK_NEMC>;
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+		clocks = <&cgu JZ4780_CLK_SMB0>;
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+		clock-frequency = <100000>;
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+		pinctrl-names = "default";
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+		pinctrl-0 = <&pins_i2c0_data>;
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 		status = "disabled";
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 	};
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+	i2c1: i2c@10051000 {
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+		compatible = "ingenic,jz4780-i2c";
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+		#address-cells = <1>;
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+		#size-cells = <0>;
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+		reg = <0x10051000 0x1000>;
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+
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+		interrupt-parent = <&intc>;
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+		interrupts = <59>;
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+
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+		clocks = <&cgu JZ4780_CLK_SMB1>;
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+		clock-frequency = <100000>;
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+		pinctrl-names = "default";
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+		pinctrl-0 = <&pins_i2c1_data>;
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+
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+		status = "disabled";
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+	};
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+
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+	i2c2: i2c@10052000 {
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+		compatible = "ingenic,jz4780-i2c";
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+		#address-cells = <1>;
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+		#size-cells = <0>;
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+		reg = <0x10052000 0x1000>;
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+
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+		interrupt-parent = <&intc>;
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+		interrupts = <58>;
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+
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+		clocks = <&cgu JZ4780_CLK_SMB2>;
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+		clock-frequency = <100000>;
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+		pinctrl-names = "default";
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+		pinctrl-0 = <&pins_i2c2_data>;
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+
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+		status = "disabled";
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+	};
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+
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+	i2c3: i2c@10053000 {
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+		compatible = "ingenic,jz4780-i2c";
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+		#address-cells = <1>;
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+		#size-cells = <0>;
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+		reg = <0x10053000 0x1000>;
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+
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+		interrupt-parent = <&intc>;
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+		interrupts = <57>;
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+
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+		clocks = <&cgu JZ4780_CLK_SMB3>;
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+		clock-frequency = <100000>;
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+		pinctrl-names = "default";
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+		pinctrl-0 = <&pins_i2c3_data>;
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+
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+		status = "disabled";
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+	};
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+
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+	i2c4: i2c@10054000 {
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+		compatible = "ingenic,jz4780-i2c";
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+		#address-cells = <1>;
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+		#size-cells = <0>;
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+		reg = <0x10054000 0x1000>;
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+
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+		interrupt-parent = <&intc>;
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+		interrupts = <56>;
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+
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+		clocks = <&cgu JZ4780_CLK_SMB4>;
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+		clock-frequency = <100000>;
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+		pinctrl-names = "default";
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+		pinctrl-0 = <&pins_i2c4_data>;
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+
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+		status = "disabled";
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+	};
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+
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+	nemc: nemc@13410000 {
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+		compatible = "ingenic,jz4780-nemc", "simple-mfd";
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+		reg = <0x13410000 0x10000>;
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+		#address-cells = <2>;
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+		#size-cells = <1>;
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+		ranges = <0 0 0x13410000 0x10000>,
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+			 <1 0 0x1b000000 0x1000000>,
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+			 <2 0 0x1a000000 0x1000000>,
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+			 <3 0 0x19000000 0x1000000>,
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+			 <4 0 0x18000000 0x1000000>,
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+			 <5 0 0x17000000 0x1000000>,
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+			 <6 0 0x16000000 0x1000000>;
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+
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+		clocks = <&cgu JZ4780_CLK_NEMC>;
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+
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+		status = "disabled";
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+
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+		efuse: efuse@d0 {
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+			reg = <0 0xd0 0x30>;
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+			compatible = "ingenic,jz4780-efuse";
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+
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+			clocks = <&cgu JZ4780_CLK_AHB2>;
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+
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+
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+			eth0_addr: eth-mac-addr@22 {
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+				reg = <0x22 0x6>;
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+			};
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+		};
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+	};
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+
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 	dma: dma@13420000 {
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 		compatible = "ingenic,jz4780-dma";
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-		reg = <0x13420000 0x10000>;
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+		reg = <0x13420000 0x400>, <0x13421000 0x40>;
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 		#dma-cells = <2>;
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442
 
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 		interrupt-parent = <&intc>;