~hc/RK356X_SDK_RELEASE.git

..	..	@@ -2,37 +2,43 @@
2	2	config MIPS
3	3	bool
4	4	default y
5		- select ARCH_BINFMT_ELF_STATE
6		- select ARCH_CLOCKSOURCE_DATA
7		- select ARCH_DISCARD_MEMBLOCK
8		- select ARCH_HAS_ELF_RANDOMIZE
	5	+ select ARCH_32BIT_OFF_T if !64BIT
	6	+ select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
	7	+ select ARCH_HAS_FORTIFY_SOURCE
	8	+ select ARCH_HAS_KCOV
	9	+ select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE if !EVA
	10	+ select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
9	11	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
	12	+ select ARCH_HAS_UBSAN_SANITIZE_ALL
10	13	select ARCH_SUPPORTS_UPROBES
11	14	select ARCH_USE_BUILTIN_BSWAP
12	15	select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
13	16	select ARCH_USE_QUEUED_RWLOCKS
14	17	select ARCH_USE_QUEUED_SPINLOCKS
	18	+ select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
15	19	select ARCH_WANT_IPC_PARSE_VERSION
16		- select BUILDTIME_EXTABLE_SORT
	20	+ select BUILDTIME_TABLE_SORT
17	21	select CLONE_BACKWARDS
	22	+ select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
18	23	select CPU_PM if CPU_IDLE
19		- select DMA_DIRECT_OPS
20	24	select GENERIC_ATOMIC64 if !64BIT
21	25	select GENERIC_CLOCKEVENTS
22	26	select GENERIC_CMOS_UPDATE
23	27	select GENERIC_CPU_AUTOPROBE
24	28	select GENERIC_GETTIMEOFDAY
	29	+ select GENERIC_IOMAP
25	30	select GENERIC_IRQ_PROBE
26	31	select GENERIC_IRQ_SHOW
	32	+ select GENERIC_ISA_DMA if EISA
27	33	select GENERIC_LIB_ASHLDI3
28	34	select GENERIC_LIB_ASHRDI3
29	35	select GENERIC_LIB_CMPDI2
30	36	select GENERIC_LIB_LSHRDI3
31	37	select GENERIC_LIB_UCMPDI2
32		- select GENERIC_PCI_IOMAP
33	38	select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
34	39	select GENERIC_SMP_IDLE_THREAD
35	40	select GENERIC_TIME_VSYSCALL
	41	+ select GUP_GET_PTE_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
36	42	select HANDLE_DOMAIN_IRQ
37	43	select HAVE_ARCH_COMPILER_H
38	44	select HAVE_ARCH_JUMP_LABEL
..	..	@@ -41,73 +47,100 @@
41	47	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if MMU && COMPAT
42	48	select HAVE_ARCH_SECCOMP_FILTER
43	49	select HAVE_ARCH_TRACEHOOK
44		- select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES && 64BIT
45		- select HAVE_CBPF_JIT if (!64BIT && !CPU_MICROMIPS)
46		- select HAVE_EBPF_JIT if (64BIT && !CPU_MICROMIPS)
	50	+ select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
	51	+ select HAVE_ASM_MODVERSIONS
	52	+ select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
47	53	select HAVE_CONTEXT_TRACKING
48		- select HAVE_COPY_THREAD_TLS
	54	+ select HAVE_TIF_NOHZ
49	55	select HAVE_C_RECORDMCOUNT
50	56	select HAVE_DEBUG_KMEMLEAK
51	57	select HAVE_DEBUG_STACKOVERFLOW
52	58	select HAVE_DMA_CONTIGUOUS
53	59	select HAVE_DYNAMIC_FTRACE
	60	+ select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
54	61	select HAVE_EXIT_THREAD
	62	+ select HAVE_FAST_GUP
55	63	select HAVE_FTRACE_MCOUNT_RECORD
56	64	select HAVE_FUNCTION_GRAPH_TRACER
57	65	select HAVE_FUNCTION_TRACER
58		- select HAVE_GENERIC_DMA_COHERENT
	66	+ select HAVE_GCC_PLUGINS
	67	+ select HAVE_GENERIC_VDSO
59	68	select HAVE_IDE
	69	+ select HAVE_IOREMAP_PROT
60	70	select HAVE_IRQ_EXIT_ON_IRQ_STACK
61	71	select HAVE_IRQ_TIME_ACCOUNTING
62	72	select HAVE_KPROBES
63	73	select HAVE_KRETPROBES
64		- select HAVE_MEMBLOCK
65		- select HAVE_MEMBLOCK_NODE_MAP
	74	+ select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
66	75	select HAVE_MOD_ARCH_SPECIFIC
67	76	select HAVE_NMI
68	77	select HAVE_OPROFILE
69	78	select HAVE_PERF_EVENTS
70	79	select HAVE_REGS_AND_STACK_ACCESS_API
71	80	select HAVE_RSEQ
	81	+ select HAVE_SPARSE_SYSCALL_NR
72	82	select HAVE_STACKPROTECTOR
73	83	select HAVE_SYSCALL_TRACEPOINTS
74	84	select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT \|\| !SMP
75		- select HAVE_GENERIC_VDSO
76	85	select IRQ_FORCED_THREADING
77		- select MODULES_USE_ELF_RELA if MODULES && 64BIT
	86	+ select ISA if EISA
78	87	select MODULES_USE_ELF_REL if MODULES
	88	+ select MODULES_USE_ELF_RELA if MODULES && 64BIT
79	89	select PERF_USE_VMALLOC
80		- select RTC_LIB if !MACH_LOONGSON64
	90	+ select PCI_MSI_ARCH_FALLBACKS if PCI_MSI
	91	+ select RTC_LIB
	92	+ select SET_FS
81	93	select SYSCTL_EXCEPTION_TRACE
82	94	select VIRT_TO_BUS
	95	+
	96	+config MIPS_FIXUP_BIGPHYS_ADDR
	97	+ bool
	98	+
	99	+config MIPS_GENERIC
	100	+ bool
	101	+
	102	+config MACH_INGENIC
	103	+ bool
	104	+ select SYS_SUPPORTS_32BIT_KERNEL
	105	+ select SYS_SUPPORTS_LITTLE_ENDIAN
	106	+ select SYS_SUPPORTS_ZBOOT
	107	+ select DMA_NONCOHERENT
	108	+ select IRQ_MIPS_CPU
	109	+ select PINCTRL
	110	+ select GPIOLIB
	111	+ select COMMON_CLK
	112	+ select GENERIC_IRQ_CHIP
	113	+ select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
	114	+ select USE_OF
	115	+ select CPU_SUPPORTS_CPUFREQ
	116	+ select MIPS_EXTERNAL_TIMER
83	117
84	118	menu "Machine selection"
85	119
86	120	choice
87	121	prompt "System type"
88		- default MIPS_GENERIC
	122	+ default MIPS_GENERIC_KERNEL
89	123
90		-config MIPS_GENERIC
	124	+config MIPS_GENERIC_KERNEL
91	125	bool "Generic board-agnostic MIPS kernel"
	126	+ select MIPS_GENERIC
92	127	select BOOT_RAW
93	128	select BUILTIN_DTB
94	129	select CEVT_R4K
95	130	select CLKSRC_MIPS_GIC
96	131	select COMMON_CLK
97		- select CPU_MIPSR2_IRQ_VI
98	132	select CPU_MIPSR2_IRQ_EI
	133	+ select CPU_MIPSR2_IRQ_VI
99	134	select CSRC_R4K
100	135	select DMA_PERDEV_COHERENT
101		- select HW_HAS_PCI
	136	+ select HAVE_PCI
102	137	select IRQ_MIPS_CPU
103		- select LIBFDT
104	138	select MIPS_AUTO_PFN_OFFSET
105	139	select MIPS_CPU_SCACHE
106	140	select MIPS_GIC
107	141	select MIPS_L1_CACHE_SHIFT_7
108	142	select NO_EXCEPT_FILL
109	143	select PCI_DRIVERS_GENERIC
110		- select PINCTRL
111	144	select SMP_UP if SMP
112	145	select SWAP_IO_SPACE
113	146	select SYS_HAS_CPU_MIPS32_R1
..	..	@@ -122,11 +155,13 @@
122	155	select SYS_SUPPORTS_HIGHMEM
123	156	select SYS_SUPPORTS_LITTLE_ENDIAN
124	157	select SYS_SUPPORTS_MICROMIPS
125		- select SYS_SUPPORTS_MIPS_CPS
126	158	select SYS_SUPPORTS_MIPS16
	159	+ select SYS_SUPPORTS_MIPS_CPS
127	160	select SYS_SUPPORTS_MULTITHREADING
128	161	select SYS_SUPPORTS_RELOCATABLE
129	162	select SYS_SUPPORTS_SMARTMIPS
	163	+ select SYS_SUPPORTS_ZBOOT
	164	+ select UHI_BOOT
130	165	select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
131	166	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
132	167	select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
..	..	@@ -147,6 +182,7 @@
147	182	select CSRC_R4K
148	183	select IRQ_MIPS_CPU
149	184	select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
	185	+ select MIPS_FIXUP_BIGPHYS_ADDR if PCI
150	186	select SYS_HAS_CPU_MIPS32_R1
151	187	select SYS_SUPPORTS_32BIT_KERNEL
152	188	select SYS_SUPPORTS_APM_EMULATION
..	..	@@ -171,7 +207,7 @@
171	207	select SYS_SUPPORTS_ZBOOT_UART16550
172	208	select GPIOLIB
173	209	select VLYNQ
174		- select HAVE_CLK
	210	+ select HAVE_LEGACY_CLK
175	211	help
176	212	Support for the Texas Instruments AR7 System-on-a-Chip
177	213	family: TNETD7100, 7200 and 7300.
..	..	@@ -199,11 +235,8 @@
199	235	select DMA_NONCOHERENT
200	236	select GPIOLIB
201	237	select PINCTRL
202		- select HAVE_CLK
203	238	select COMMON_CLK
204		- select CLKDEV_LOOKUP
205	239	select IRQ_MIPS_CPU
206		- select MIPS_MACHINE
207	240	select SYS_HAS_CPU_MIPS32_R2
208	241	select SYS_HAS_EARLY_PRINTK
209	242	select SYS_SUPPORTS_32BIT_KERNEL
..	..	@@ -258,7 +291,7 @@
258	291	select CEVT_R4K
259	292	select CSRC_R4K
260	293	select DMA_NONCOHERENT
261		- select HW_HAS_PCI
	294	+ select HAVE_PCI
262	295	select IRQ_MIPS_CPU
263	296	select SYS_HAS_CPU_MIPS32_R1
264	297	select NO_EXCEPT_FILL
..	..	@@ -274,7 +307,7 @@
274	307	select BCM47XX_SPROM
275	308	select BCM47XX_SSB if !BCM47XX_BCMA
276	309	help
277		- Support for BCM47XX based boards
	310	+ Support for BCM47XX based boards
278	311
279	312	config BCM63XX
280	313	bool "Broadcom BCM63XX based boards"
..	..	@@ -292,11 +325,11 @@
292	325	select SYS_HAS_CPU_BMIPS4380
293	326	select SWAP_IO_SPACE
294	327	select GPIOLIB
295		- select HAVE_CLK
296	328	select MIPS_L1_CACHE_SHIFT_4
297	329	select CLKDEV_LOOKUP
	330	+ select HAVE_LEGACY_CLK
298	331	help
299		- Support for BCM63XX based boards
	332	+ Support for BCM63XX based boards
300	333
301	334	config MIPS_COBALT
302	335	bool "Cobalt Server"
..	..	@@ -304,13 +337,12 @@
304	337	select CSRC_R4K
305	338	select CEVT_GT641XX
306	339	select DMA_NONCOHERENT
307		- select HW_HAS_PCI
	340	+ select FORCE_PCI
308	341	select I8253
309	342	select I8259
310	343	select IRQ_MIPS_CPU
311	344	select IRQ_GT641XX
312	345	select PCI_GT64XXX_PCI0
313		- select PCI
314	346	select SYS_HAS_CPU_NEVADA
315	347	select SYS_HAS_EARLY_PRINTK
316	348	select SYS_SUPPORTS_32BIT_KERNEL
..	..	@@ -357,8 +389,11 @@
357	389
358	390	config MACH_JAZZ
359	391	bool "Jazz family of machines"
	392	+ select ARC_MEMORY
	393	+ select ARC_PROMLIB
360	394	select ARCH_MIGHT_HAVE_PC_PARPORT
361	395	select ARCH_MIGHT_HAVE_PC_SERIO
	396	+ select DMA_OPS
362	397	select FW_ARC
363	398	select FW_ARC32
364	399	select ARCH_MAY_HAVE_PC_FDC
..	..	@@ -376,25 +411,18 @@
376	411	select SYS_SUPPORTS_64BIT_KERNEL
377	412	select SYS_SUPPORTS_100HZ
378	413	help
379		- This a family of machines based on the MIPS R4030 chipset which was
380		- used by several vendors to build RISC/os and Windows NT workstations.
381		- Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
382		- Olivetti M700-10 workstations.
	414	+ This a family of machines based on the MIPS R4030 chipset which was
	415	+ used by several vendors to build RISC/os and Windows NT workstations.
	416	+ Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
	417	+ Olivetti M700-10 workstations.
383	418
384		-config MACH_INGENIC
	419	+config MACH_INGENIC_SOC
385	420	bool "Ingenic SoC based machines"
386		- select SYS_SUPPORTS_32BIT_KERNEL
387		- select SYS_SUPPORTS_LITTLE_ENDIAN
	421	+ select MIPS_GENERIC
	422	+ select MACH_INGENIC
388	423	select SYS_SUPPORTS_ZBOOT_UART16550
389		- select DMA_NONCOHERENT
390		- select IRQ_MIPS_CPU
391		- select PINCTRL
392		- select GPIOLIB
393		- select COMMON_CLK
394		- select GENERIC_IRQ_CHIP
395		- select BUILTIN_DTB
396		- select USE_OF
397		- select LIBFDT
	424	+ select CPU_SUPPORTS_CPUFREQ
	425	+ select MIPS_EXTERNAL_TIMER
398	426
399	427	config LANTIQ
400	428	bool "Lantiq based platforms"
..	..	@@ -414,31 +442,15 @@
414	442	select SWAP_IO_SPACE
415	443	select BOOT_RAW
416	444	select CLKDEV_LOOKUP
	445	+ select HAVE_LEGACY_CLK
417	446	select USE_OF
418	447	select PINCTRL
419	448	select PINCTRL_LANTIQ
420	449	select ARCH_HAS_RESET_CONTROLLER
421	450	select RESET_CONTROLLER
422	451
423		-config LASAT
424		- bool "LASAT Networks platforms"
425		- select CEVT_R4K
426		- select CRC32
427		- select CSRC_R4K
428		- select DMA_NONCOHERENT
429		- select SYS_HAS_EARLY_PRINTK
430		- select HW_HAS_PCI
431		- select IRQ_MIPS_CPU
432		- select PCI_GT64XXX_PCI0
433		- select MIPS_NILE4
434		- select R5000_CPU_SCACHE
435		- select SYS_HAS_CPU_R5000
436		- select SYS_SUPPORTS_32BIT_KERNEL
437		- select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
438		- select SYS_SUPPORTS_LITTLE_ENDIAN
439		-
440	452	config MACH_LOONGSON32
441		- bool "Loongson-1 family of machines"
	453	+ bool "Loongson 32-bit family of machines"
442	454	select SYS_SUPPORTS_ZBOOT
443	455	help
444	456	This enables support for the Loongson-1 family of machines.
..	..	@@ -447,18 +459,54 @@
447	459	the Institute of Computing Technology (ICT), Chinese Academy of
448	460	Sciences (CAS).
449	461
450		-config MACH_LOONGSON64
451		- bool "Loongson-2/3 family of machines"
	462	+config MACH_LOONGSON2EF
	463	+ bool "Loongson-2E/F family of machines"
452	464	select SYS_SUPPORTS_ZBOOT
	465	+ help
	466	+ This enables the support of early Loongson-2E/F family of machines.
	467	+
	468	+config MACH_LOONGSON64
	469	+ bool "Loongson 64-bit family of machines"
	470	+ select ARCH_SPARSEMEM_ENABLE
	471	+ select ARCH_MIGHT_HAVE_PC_PARPORT
	472	+ select ARCH_MIGHT_HAVE_PC_SERIO
	473	+ select GENERIC_ISA_DMA_SUPPORT_BROKEN
	474	+ select BOOT_ELF32
	475	+ select BOARD_SCACHE
	476	+ select CSRC_R4K
	477	+ select CEVT_R4K
	478	+ select CPU_HAS_WB
	479	+ select FORCE_PCI
	480	+ select ISA
	481	+ select I8259
	482	+ select IRQ_MIPS_CPU
	483	+ select NO_EXCEPT_FILL
	484	+ select NR_CPUS_DEFAULT_64
	485	+ select USE_GENERIC_EARLY_PRINTK_8250
	486	+ select PCI_DRIVERS_GENERIC
	487	+ select SYS_HAS_CPU_LOONGSON64
	488	+ select SYS_HAS_EARLY_PRINTK
	489	+ select SYS_SUPPORTS_SMP
	490	+ select SYS_SUPPORTS_HOTPLUG_CPU
	491	+ select SYS_SUPPORTS_NUMA
	492	+ select SYS_SUPPORTS_64BIT_KERNEL
	493	+ select SYS_SUPPORTS_HIGHMEM
	494	+ select SYS_SUPPORTS_LITTLE_ENDIAN
	495	+ select SYS_SUPPORTS_ZBOOT
	496	+ select ZONE_DMA32
	497	+ select NUMA
	498	+ select SMP
	499	+ select COMMON_CLK
	500	+ select USE_OF
	501	+ select BUILTIN_DTB
	502	+ select PCI_HOST_GENERIC
453	503	help
454	504	This enables the support of Loongson-2/3 family of machines.
455	505
456		- Loongson-2 is a family of single-core CPUs and Loongson-3 is a
457		- family of multi-core CPUs. They are both 64-bit general-purpose
458		- MIPS-compatible CPUs. Loongson-2/3 are developed by the Institute
459		- of Computing Technology (ICT), Chinese Academy of Sciences (CAS)
460		- in the People's Republic of China. The chief architect is Professor
461		- Weiwu Hu.
	506	+ Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
	507	+ GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
	508	+ and Loongson-2F which will be removed), developed by the Institute
	509	+ of Computing Technology (ICT), Chinese Academy of Sciences (CAS).
462	510
463	511	config MACH_PISTACHIO
464	512	bool "IMG Pistachio SoC based boards"
..	..	@@ -471,7 +519,6 @@
471	519	select DMA_NONCOHERENT
472	520	select GPIOLIB
473	521	select IRQ_MIPS_CPU
474		- select LIBFDT
475	522	select MFD_SYSCON
476	523	select MIPS_CPU_SCACHE
477	524	select MIPS_GIC
..	..	@@ -499,22 +546,22 @@
499	546	select BOOT_RAW
500	547	select BUILTIN_DTB
501	548	select CEVT_R4K
502		- select CSRC_R4K
503	549	select CLKSRC_MIPS_GIC
504	550	select COMMON_CLK
	551	+ select CSRC_R4K
505	552	select DMA_MAYBE_COHERENT
506	553	select GENERIC_ISA_DMA
507	554	select HAVE_PCSPKR_PLATFORM
508		- select IRQ_MIPS_CPU
509		- select MIPS_GIC
510		- select HW_HAS_PCI
	555	+ select HAVE_PCI
511	556	select I8253
512	557	select I8259
	558	+ select IRQ_MIPS_CPU
513	559	select MIPS_BONITO64
514	560	select MIPS_CPU_SCACHE
	561	+ select MIPS_GIC
515	562	select MIPS_L1_CACHE_SHIFT_6
516		- select PCI_GT64XXX_PCI0
517	563	select MIPS_MSC
	564	+ select PCI_GT64XXX_PCI0
518	565	select SMP_UP if SMP
519	566	select SWAP_IO_SPACE
520	567	select SYS_HAS_CPU_MIPS32_R1
..	..	@@ -533,19 +580,17 @@
533	580	select SYS_SUPPORTS_HIGHMEM
534	581	select SYS_SUPPORTS_LITTLE_ENDIAN
535	582	select SYS_SUPPORTS_MICROMIPS
	583	+ select SYS_SUPPORTS_MIPS16
536	584	select SYS_SUPPORTS_MIPS_CMP
537	585	select SYS_SUPPORTS_MIPS_CPS
538		- select SYS_SUPPORTS_MIPS16
539	586	select SYS_SUPPORTS_MULTITHREADING
	587	+ select SYS_SUPPORTS_RELOCATABLE
540	588	select SYS_SUPPORTS_SMARTMIPS
541	589	select SYS_SUPPORTS_VPE_LOADER
542	590	select SYS_SUPPORTS_ZBOOT
543		- select SYS_SUPPORTS_RELOCATABLE
544	591	select USE_OF
545		- select LIBFDT
	592	+ select WAR_ICACHE_REFILLS
546	593	select ZONE_DMA32 if 64BIT
547		- select BUILTIN_DTB
548		- select LIBFDT
549	594	help
550	595	This enables support for the MIPS Technologies Malta evaluation
551	596	board.
..	..	@@ -558,13 +603,6 @@
558	603	Microchip PIC32 is a family of general-purpose 32 bit MIPS core
559	604	microcontrollers.
560	605
561		-config NEC_MARKEINS
562		- bool "NEC EMMA2RH Mark-eins board"
563		- select SOC_EMMA2RH
564		- select HW_HAS_PCI
565		- help
566		- This enables support for the NEC Electronics Mark-eins boards.
567		-
568	606	config MACH_VR41XX
569	607	bool "NEC VR4100 series based machines"
570	608	select CEVT_R4K
..	..	@@ -572,43 +610,6 @@
572	610	select SYS_HAS_CPU_VR41XX
573	611	select SYS_SUPPORTS_MIPS16
574	612	select GPIOLIB
575		-
576		-config NXP_STB220
577		- bool "NXP STB220 board"
578		- select SOC_PNX833X
579		- help
580		- Support for NXP Semiconductors STB220 Development Board.
581		-
582		-config NXP_STB225
583		- bool "NXP 225 board"
584		- select SOC_PNX833X
585		- select SOC_PNX8335
586		- help
587		- Support for NXP Semiconductors STB225 Development Board.
588		-
589		-config PMC_MSP
590		- bool "PMC-Sierra MSP chipsets"
591		- select CEVT_R4K
592		- select CSRC_R4K
593		- select DMA_NONCOHERENT
594		- select SWAP_IO_SPACE
595		- select NO_EXCEPT_FILL
596		- select BOOT_RAW
597		- select SYS_HAS_CPU_MIPS32_R1
598		- select SYS_HAS_CPU_MIPS32_R2
599		- select SYS_SUPPORTS_32BIT_KERNEL
600		- select SYS_SUPPORTS_BIG_ENDIAN
601		- select SYS_SUPPORTS_MIPS16
602		- select IRQ_MIPS_CPU
603		- select SERIAL_8250
604		- select SERIAL_8250_CONSOLE
605		- select USB_EHCI_BIG_ENDIAN_MMIO
606		- select USB_EHCI_BIG_ENDIAN_DESC
607		- help
608		- This adds support for the PMC-Sierra family of Multi-Service
609		- Processor System-On-A-Chips. These parts include a number
610		- of integrated peripherals, interfaces and DSPs in addition to
611		- a variety of MIPS cores.
612	613
613	614	config RALINK
614	615	bool "Ralink based machines"
..	..	@@ -623,6 +624,7 @@
623	624	select SYS_SUPPORTS_32BIT_KERNEL
624	625	select SYS_SUPPORTS_LITTLE_ENDIAN
625	626	select SYS_SUPPORTS_MIPS16
	627	+ select SYS_SUPPORTS_ZBOOT
626	628	select SYS_HAS_EARLY_PRINTK
627	629	select CLKDEV_LOOKUP
628	630	select ARCH_HAS_RESET_CONTROLLER
..	..	@@ -630,6 +632,8 @@
630	632
631	633	config SGI_IP22
632	634	bool "SGI IP22 (Indy/Indigo2)"
	635	+ select ARC_MEMORY
	636	+ select ARC_PROMLIB
633	637	select FW_ARC
634	638	select FW_ARC32
635	639	select ARCH_MIGHT_HAVE_PC_SERIO
..	..	@@ -638,7 +642,7 @@
638	642	select CSRC_R4K
639	643	select DEFAULT_SGI_PARTITION
640	644	select DMA_NONCOHERENT
641		- select HW_HAS_EISA
	645	+ select HAVE_EISA
642	646	select I8253
643	647	select I8259
644	648	select IP22_CPU_SCACHE
..	..	@@ -653,17 +657,13 @@
653	657	select SWAP_IO_SPACE
654	658	select SYS_HAS_CPU_R4X00
655	659	select SYS_HAS_CPU_R5000
656		- #
657		- # Disable EARLY_PRINTK for now since it leads to overwritten prom
658		- # memory during early boot on some machines.
659		- #
660		- # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
661		- # for a more details discussion
662		- #
663		- # select SYS_HAS_EARLY_PRINTK
	660	+ select SYS_HAS_EARLY_PRINTK
664	661	select SYS_SUPPORTS_32BIT_KERNEL
665	662	select SYS_SUPPORTS_64BIT_KERNEL
666	663	select SYS_SUPPORTS_BIG_ENDIAN
	664	+ select WAR_R4600_V1_INDEX_ICACHEOP
	665	+ select WAR_R4600_V1_HIT_CACHEOP
	666	+ select WAR_R4600_V2_HIT_CACHEOP
667	667	select MIPS_L1_CACHE_SHIFT_7
668	668	help
669	669	This are the SGI Indy, Challenge S and Indigo2, as well as certain
..	..	@@ -673,19 +673,27 @@
673	673	config SGI_IP27
674	674	bool "SGI IP27 (Origin200/2000)"
675	675	select ARCH_HAS_PHYS_TO_DMA
	676	+ select ARCH_SPARSEMEM_ENABLE
676	677	select FW_ARC
677	678	select FW_ARC64
	679	+ select ARC_CMDLINE_ONLY
678	680	select BOOT_ELF64
679	681	select DEFAULT_SGI_PARTITION
680	682	select SYS_HAS_EARLY_PRINTK
681		- select HW_HAS_PCI
	683	+ select HAVE_PCI
	684	+ select IRQ_MIPS_CPU
	685	+ select IRQ_DOMAIN_HIERARCHY
682	686	select NR_CPUS_DEFAULT_64
	687	+ select PCI_DRIVERS_GENERIC
	688	+ select PCI_XTALK_BRIDGE
683	689	select SYS_HAS_CPU_R10000
684	690	select SYS_SUPPORTS_64BIT_KERNEL
685	691	select SYS_SUPPORTS_BIG_ENDIAN
686	692	select SYS_SUPPORTS_NUMA
687	693	select SYS_SUPPORTS_SMP
	694	+ select WAR_R10000_LLSC
688	695	select MIPS_L1_CACHE_SHIFT_7
	696	+ select NUMA
689	697	help
690	698	This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
691	699	workstations. To compile a Linux kernel that runs on these, say Y
..	..	@@ -693,6 +701,8 @@
693	701
694	702	config SGI_IP28
695	703	bool "SGI IP28 (Indigo2 R10k)"
	704	+ select ARC_MEMORY
	705	+ select ARC_PROMLIB
696	706	select FW_ARC
697	707	select FW_ARC64
698	708	select ARCH_MIGHT_HAVE_PC_SERIO
..	..	@@ -703,7 +713,7 @@
703	713	select DMA_NONCOHERENT
704	714	select GENERIC_ISA_DMA_SUPPORT_BROKEN
705	715	select IRQ_MIPS_CPU
706		- select HW_HAS_EISA
	716	+ select HAVE_EISA
707	717	select I8253
708	718	select I8259
709	719	select SGI_HAS_I8042
..	..	@@ -714,23 +724,47 @@
714	724	select SGI_HAS_ZILOG
715	725	select SWAP_IO_SPACE
716	726	select SYS_HAS_CPU_R10000
717		- #
718		- # Disable EARLY_PRINTK for now since it leads to overwritten prom
719		- # memory during early boot on some machines.
720		- #
721		- # See http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20091119164009.GA15038%40deprecation.cyrius.com
722		- # for a more details discussion
723		- #
724		- # select SYS_HAS_EARLY_PRINTK
	727	+ select SYS_HAS_EARLY_PRINTK
725	728	select SYS_SUPPORTS_64BIT_KERNEL
726	729	select SYS_SUPPORTS_BIG_ENDIAN
	730	+ select WAR_R10000_LLSC
727	731	select MIPS_L1_CACHE_SHIFT_7
728		- help
729		- This is the SGI Indigo2 with R10000 processor. To compile a Linux
730		- kernel that runs on these, say Y here.
	732	+ help
	733	+ This is the SGI Indigo2 with R10000 processor. To compile a Linux
	734	+ kernel that runs on these, say Y here.
	735	+
	736	+config SGI_IP30
	737	+ bool "SGI IP30 (Octane/Octane2)"
	738	+ select ARCH_HAS_PHYS_TO_DMA
	739	+ select FW_ARC
	740	+ select FW_ARC64
	741	+ select BOOT_ELF64
	742	+ select CEVT_R4K
	743	+ select CSRC_R4K
	744	+ select SYNC_R4K if SMP
	745	+ select ZONE_DMA32
	746	+ select HAVE_PCI
	747	+ select IRQ_MIPS_CPU
	748	+ select IRQ_DOMAIN_HIERARCHY
	749	+ select NR_CPUS_DEFAULT_2
	750	+ select PCI_DRIVERS_GENERIC
	751	+ select PCI_XTALK_BRIDGE
	752	+ select SYS_HAS_EARLY_PRINTK
	753	+ select SYS_HAS_CPU_R10000
	754	+ select SYS_SUPPORTS_64BIT_KERNEL
	755	+ select SYS_SUPPORTS_BIG_ENDIAN
	756	+ select SYS_SUPPORTS_SMP
	757	+ select WAR_R10000_LLSC
	758	+ select MIPS_L1_CACHE_SHIFT_7
	759	+ select ARC_MEMORY
	760	+ help
	761	+ These are the SGI Octane and Octane2 graphics workstations. To
	762	+ compile a Linux kernel that runs on these, say Y here.
731	763
732	764	config SGI_IP32
733	765	bool "SGI IP32 (O2)"
	766	+ select ARC_MEMORY
	767	+ select ARC_PROMLIB
734	768	select ARCH_HAS_PHYS_TO_DMA
735	769	select FW_ARC
736	770	select FW_ARC32
..	..	@@ -738,7 +772,7 @@
738	772	select CEVT_R4K
739	773	select CSRC_R4K
740	774	select DMA_NONCOHERENT
741		- select HW_HAS_PCI
	775	+ select HAVE_PCI
742	776	select IRQ_MIPS_CPU
743	777	select R5000_CPU_SCACHE
744	778	select RM7000_CPU_SCACHE
..	..	@@ -748,6 +782,7 @@
748	782	select SYS_HAS_CPU_NEVADA
749	783	select SYS_SUPPORTS_64BIT_KERNEL
750	784	select SYS_SUPPORTS_BIG_ENDIAN
	785	+ select WAR_ICACHE_REFILLS
751	786	help
752	787	If you want this kernel to run on SGI O2 workstation, say Y here.
753	788
..	..	@@ -838,6 +873,8 @@
838	873
839	874	config SNI_RM
840	875	bool "SNI RM200/300/400"
	876	+ select ARC_MEMORY
	877	+ select ARC_PROMLIB
841	878	select FW_ARC if CPU_LITTLE_ENDIAN
842	879	select FW_ARC32 if CPU_LITTLE_ENDIAN
843	880	select FW_SNIPROM if CPU_BIG_ENDIAN
..	..	@@ -850,9 +887,9 @@
850	887	select DEFAULT_SGI_PARTITION if CPU_BIG_ENDIAN
851	888	select DMA_NONCOHERENT
852	889	select GENERIC_ISA_DMA
	890	+ select HAVE_EISA
853	891	select HAVE_PCSPKR_PLATFORM
854		- select HW_HAS_EISA
855		- select HW_HAS_PCI
	892	+ select HAVE_PCI
856	893	select IRQ_MIPS_CPU
857	894	select I8253
858	895	select I8259
..	..	@@ -869,6 +906,7 @@
869	906	select SYS_SUPPORTS_BIG_ENDIAN
870	907	select SYS_SUPPORTS_HIGHMEM
871	908	select SYS_SUPPORTS_LITTLE_ENDIAN
	909	+ select WAR_R4600_V2_HIT_CACHEOP
872	910	help
873	911	The SNI RM200/300/400 are MIPS-based machines manufactured by
874	912	Siemens Nixdorf Informationssysteme (SNI), parent company of Pyramid
..	..	@@ -880,13 +918,14 @@
880	918
881	919	config MACH_TX49XX
882	920	bool "Toshiba TX49 series based machines"
	921	+ select WAR_TX49XX_ICACHE_INDEX_INV
883	922
884	923	config MIKROTIK_RB532
885	924	bool "Mikrotik RB532 boards"
886	925	select CEVT_R4K
887	926	select CSRC_R4K
888	927	select DMA_NONCOHERENT
889		- select HW_HAS_PCI
	928	+ select HAVE_PCI
890	929	select IRQ_MIPS_CPU
891	930	select SYS_HAS_CPU_MIPS32_R1
892	931	select SYS_SUPPORTS_32BIT_KERNEL
..	..	@@ -903,7 +942,7 @@
903	942	bool "Cavium Networks Octeon SoC based boards"
904	943	select CEVT_R4K
905	944	select ARCH_HAS_PHYS_TO_DMA
906		- select HAS_RAPIDIO
	945	+ select HAVE_RAPIDIO
907	946	select PHYS_ADDR_T_64BIT
908	947	select SYS_SUPPORTS_64BIT_KERNEL
909	948	select SYS_SUPPORTS_BIG_ENDIAN
..	..	@@ -913,11 +952,13 @@
913	952	select SYS_SUPPORTS_HOTPLUG_CPU if CPU_BIG_ENDIAN
914	953	select SYS_HAS_EARLY_PRINTK
915	954	select SYS_HAS_CPU_CAVIUM_OCTEON
916		- select HW_HAS_PCI
	955	+ select HAVE_PCI
	956	+ select HAVE_PLAT_DELAY
	957	+ select HAVE_PLAT_FW_INIT_CMDLINE
	958	+ select HAVE_PLAT_MEMCPY
917	959	select ZONE_DMA32
918	960	select HOLES_IN_ZONE
919	961	select GPIOLIB
920		- select LIBFDT
921	962	select USE_OF
922	963	select ARCH_SPARSEMEM_ENABLE
923	964	select SYS_SUPPORTS_SMP
..	..	@@ -946,7 +987,7 @@
946	987	select NLM_COMMON
947	988	select SYS_HAS_CPU_XLR
948	989	select SYS_SUPPORTS_SMP
949		- select HW_HAS_PCI
	990	+ select HAVE_PCI
950	991	select SWAP_IO_SPACE
951	992	select SYS_SUPPORTS_32BIT_KERNEL
952	993	select SYS_SUPPORTS_64BIT_KERNEL
..	..	@@ -972,7 +1013,7 @@
972	1013	select NLM_COMMON
973	1014	select SYS_HAS_CPU_XLP
974	1015	select SYS_SUPPORTS_SMP
975		- select HW_HAS_PCI
	1016	+ select HAVE_PCI
976	1017	select SYS_SUPPORTS_32BIT_KERNEL
977	1018	select SYS_SUPPORTS_64BIT_KERNEL
978	1019	select PHYS_ADDR_T_64BIT
..	..	@@ -994,24 +1035,6 @@
994	1035	This board is based on Netlogic XLP Processor.
995	1036	Say Y here if you have a XLP based board.
996	1037
997		-config MIPS_PARAVIRT
998		- bool "Para-Virtualized guest system"
999		- select CEVT_R4K
1000		- select CSRC_R4K
1001		- select SYS_SUPPORTS_64BIT_KERNEL
1002		- select SYS_SUPPORTS_32BIT_KERNEL
1003		- select SYS_SUPPORTS_BIG_ENDIAN
1004		- select SYS_SUPPORTS_SMP
1005		- select NR_CPUS_DEFAULT_4
1006		- select SYS_HAS_EARLY_PRINTK
1007		- select SYS_HAS_CPU_MIPS32_R2
1008		- select SYS_HAS_CPU_MIPS64_R2
1009		- select SYS_HAS_CPU_CAVIUM_OCTEON
1010		- select HW_HAS_PCI
1011		- select SWAP_IO_SPACE
1012		- help
1013		- This option supports guest running under ????
1014		-
1015	1038	endchoice
1016	1039
1017	1040	source "arch/mips/alchemy/Kconfig"
..	..	@@ -1021,32 +1044,23 @@
1021	1044	source "arch/mips/bcm63xx/Kconfig"
1022	1045	source "arch/mips/bmips/Kconfig"
1023	1046	source "arch/mips/generic/Kconfig"
	1047	+source "arch/mips/ingenic/Kconfig"
1024	1048	source "arch/mips/jazz/Kconfig"
1025		-source "arch/mips/jz4740/Kconfig"
1026	1049	source "arch/mips/lantiq/Kconfig"
1027		-source "arch/mips/lasat/Kconfig"
1028	1050	source "arch/mips/pic32/Kconfig"
1029	1051	source "arch/mips/pistachio/Kconfig"
1030		-source "arch/mips/pmcs-msp71xx/Kconfig"
1031	1052	source "arch/mips/ralink/Kconfig"
1032	1053	source "arch/mips/sgi-ip27/Kconfig"
1033	1054	source "arch/mips/sibyte/Kconfig"
1034	1055	source "arch/mips/txx9/Kconfig"
1035	1056	source "arch/mips/vr41xx/Kconfig"
1036	1057	source "arch/mips/cavium-octeon/Kconfig"
	1058	+source "arch/mips/loongson2ef/Kconfig"
1037	1059	source "arch/mips/loongson32/Kconfig"
1038	1060	source "arch/mips/loongson64/Kconfig"
1039	1061	source "arch/mips/netlogic/Kconfig"
1040		-source "arch/mips/paravirt/Kconfig"
1041	1062
1042	1063	endmenu
1043		-
1044		-config RWSEM_GENERIC_SPINLOCK
1045		- bool
1046		- default y
1047		-
1048		-config RWSEM_XCHGADD_ALGORITHM
1049		- bool
1050	1064
1051	1065	config GENERIC_HWEIGHT
1052	1066	bool
..	..	@@ -1097,6 +1111,7 @@
1097	1111	bool
1098	1112
1099	1113	config CSRC_R4K
	1114	+ select CLOCKSOURCE_WATCHDOG if CPU_FREQ
1100	1115	bool
1101	1116
1102	1117	config CSRC_SB1250
..	..	@@ -1116,21 +1131,30 @@
1116	1131	bool
1117	1132
1118	1133	config DMA_MAYBE_COHERENT
	1134	+ select ARCH_HAS_DMA_COHERENCE_H
1119	1135	select DMA_NONCOHERENT
1120	1136	bool
1121	1137
1122	1138	config DMA_PERDEV_COHERENT
1123	1139	bool
1124		- select DMA_MAYBE_COHERENT
	1140	+ select ARCH_HAS_SETUP_DMA_OPS
	1141	+ select DMA_NONCOHERENT
1125	1142
1126	1143	config DMA_NONCOHERENT
1127	1144	bool
	1145	+ #
	1146	+ # MIPS allows mixing "slightly different" Cacheability and Coherency
	1147	+ # Attribute bits. It is believed that the uncached access through
	1148	+ # KSEG1 and the implementation specific "uncached accelerated" used
	1149	+ # by pgprot_writcombine can be mixed, and the latter sometimes provides
	1150	+ # significant advantages.
	1151	+ #
	1152	+ select ARCH_HAS_DMA_WRITE_COMBINE
	1153	+ select ARCH_HAS_DMA_PREP_COHERENT
1128	1154	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
1129		- select ARCH_HAS_SYNC_DMA_FOR_CPU
1130		- select NEED_DMA_MAP_STATE
	1155	+ select ARCH_HAS_DMA_SET_UNCACHED
1131	1156	select DMA_NONCOHERENT_MMAP
1132		- select DMA_NONCOHERENT_CACHE_SYNC
1133		- select DMA_NONCOHERENT_OPS
	1157	+ select NEED_DMA_MAP_STATE
1134	1158
1135	1159	config SYS_HAS_EARLY_PRINTK
1136	1160	bool
..	..	@@ -1144,20 +1168,14 @@
1144	1168	config MIPS_MSC
1145	1169	bool
1146	1170
1147		-config MIPS_NILE4
1148		- bool
1149		-
1150	1171	config SYNC_R4K
1151	1172	bool
1152		-
1153		-config MIPS_MACHINE
1154		- def_bool n
1155	1173
1156	1174	config NO_IOPORT_MAP
1157	1175	def_bool n
1158	1176
1159	1177	config GENERIC_CSUM
1160		- bool
	1178	+ def_bool CPU_NO_LOAD_STORE_LR
1161	1179
1162	1180	config GENERIC_ISA_DMA
1163	1181	bool
..	..	@@ -1168,6 +1186,15 @@
1168	1186	bool
1169	1187	select GENERIC_ISA_DMA
1170	1188
	1189	+config HAVE_PLAT_DELAY
	1190	+ bool
	1191	+
	1192	+config HAVE_PLAT_FW_INIT_CMDLINE
	1193	+ bool
	1194	+
	1195	+config HAVE_PLAT_MEMCPY
	1196	+ bool
	1197	+
1171	1198	config ISA_DMA_API
1172	1199	bool
1173	1200
..	..	@@ -1177,9 +1204,9 @@
1177	1204	config SYS_SUPPORTS_RELOCATABLE
1178	1205	bool
1179	1206	help
1180		- Selected if the platform supports relocating the kernel.
1181		- The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
1182		- to allow access to command line and entropy sources.
	1207	+ Selected if the platform supports relocating the kernel.
	1208	+ The platform must provide plat_get_fdt() if it selects CONFIG_USE_OF
	1209	+ to allow access to command line and entropy sources.
1183	1210
1184	1211	config MIPS_CBPF_JIT
1185	1212	def_bool y
..	..	@@ -1228,7 +1255,7 @@
1228	1255
1229	1256	config SYS_SUPPORTS_HUGETLBFS
1230	1257	bool
1231		- depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
	1258	+ depends on CPU_SUPPORTS_HUGEPAGES
1232	1259	default y
1233	1260
1234	1261	config MIPS_HUGE_TLB_SUPPORT
..	..	@@ -1252,37 +1279,11 @@
1252	1279	config PCI_GT64XXX_PCI0
1253	1280	bool
1254	1281
	1282	+config PCI_XTALK_BRIDGE
	1283	+ bool
	1284	+
1255	1285	config NO_EXCEPT_FILL
1256	1286	bool
1257		-
1258		-config SOC_EMMA2RH
1259		- bool
1260		- select CEVT_R4K
1261		- select CSRC_R4K
1262		- select DMA_NONCOHERENT
1263		- select IRQ_MIPS_CPU
1264		- select SWAP_IO_SPACE
1265		- select SYS_HAS_CPU_R5500
1266		- select SYS_SUPPORTS_32BIT_KERNEL
1267		- select SYS_SUPPORTS_64BIT_KERNEL
1268		- select SYS_SUPPORTS_BIG_ENDIAN
1269		-
1270		-config SOC_PNX833X
1271		- bool
1272		- select CEVT_R4K
1273		- select CSRC_R4K
1274		- select IRQ_MIPS_CPU
1275		- select DMA_NONCOHERENT
1276		- select SYS_HAS_CPU_MIPS32_R2
1277		- select SYS_SUPPORTS_32BIT_KERNEL
1278		- select SYS_SUPPORTS_LITTLE_ENDIAN
1279		- select SYS_SUPPORTS_BIG_ENDIAN
1280		- select SYS_SUPPORTS_MIPS16
1281		- select CPU_MIPSR2_IRQ_VI
1282		-
1283		-config SOC_PNX8335
1284		- bool
1285		- select SOC_PNX833X
1286	1287
1287	1288	config MIPS_SPRAM
1288	1289	bool
..	..	@@ -1340,7 +1341,7 @@
1340	1341	default "4" if MIPS_L1_CACHE_SHIFT_4
1341	1342	default "5"
1342	1343
1343		-config HAVE_STD_PC_SERIAL_PORT
	1344	+config ARC_CMDLINE_ONLY
1344	1345	bool
1345	1346
1346	1347	config ARC_CONSOLE
..	..	@@ -1349,13 +1350,9 @@
1349	1350
1350	1351	config ARC_MEMORY
1351	1352	bool
1352		- depends on MACH_JAZZ \|\| SNI_RM \|\| SGI_IP32
1353		- default y
1354	1353
1355	1354	config ARC_PROMLIB
1356	1355	bool
1357		- depends on MACH_JAZZ \|\| SNI_RM \|\| SGI_IP22 \|\| SGI_IP28 \|\| SGI_IP32
1358		- default y
1359	1356
1360	1357	config FW_ARC64
1361	1358	bool
..	..	@@ -1369,46 +1366,81 @@
1369	1366	prompt "CPU type"
1370	1367	default CPU_R4X00
1371	1368
1372		-config CPU_LOONGSON3
1373		- bool "Loongson 3 CPU"
1374		- depends on SYS_HAS_CPU_LOONGSON3
	1369	+config CPU_LOONGSON64
	1370	+ bool "Loongson 64-bit CPU"
	1371	+ depends on SYS_HAS_CPU_LOONGSON64
1375	1372	select ARCH_HAS_PHYS_TO_DMA
	1373	+ select CPU_MIPSR2
	1374	+ select CPU_HAS_PREFETCH
1376	1375	select CPU_SUPPORTS_64BIT_KERNEL
1377	1376	select CPU_SUPPORTS_HIGHMEM
1378	1377	select CPU_SUPPORTS_HUGEPAGES
	1378	+ select CPU_SUPPORTS_MSA
	1379	+ select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
	1380	+ select CPU_MIPSR2_IRQ_VI
1379	1381	select WEAK_ORDERING
1380	1382	select WEAK_REORDERING_BEYOND_LLSC
	1383	+ select MIPS_ASID_BITS_VARIABLE
1381	1384	select MIPS_PGD_C0_CONTEXT
1382	1385	select MIPS_L1_CACHE_SHIFT_6
1383	1386	select MIPS_FP_SUPPORT
1384	1387	select GPIOLIB
1385	1388	select SWIOTLB
	1389	+ select HAVE_KVM
1386	1390	help
1387		- The Loongson 3 processor implements the MIPS64R2 instruction
1388		- set with many extensions.
	1391	+ The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
	1392	+ cores implements the MIPS64R2 instruction set with many extensions,
	1393	+ including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
	1394	+ 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
	1395	+ Loongson-2E/2F is not covered here and will be removed in future.
1389	1396
1390	1397	config LOONGSON3_ENHANCEMENT
1391		- bool "New Loongson 3 CPU Enhancements"
	1398	+ bool "New Loongson-3 CPU Enhancements"
1392	1399	default n
1393		- select CPU_MIPSR2
1394		- select CPU_HAS_PREFETCH
1395		- depends on CPU_LOONGSON3
	1400	+ depends on CPU_LOONGSON64
1396	1401	help
1397		- New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A
	1402	+ New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1398	1403	R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1399		- FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User
	1404	+ FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1400	1405	Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1401	1406	Fast TLB refill support, etc.
1402	1407
1403	1408	This option enable those enhancements which are not probed at run
1404	1409	time. If you want a generic kernel to run on all Loongson 3 machines,
1405	1410	please say 'N' here. If you want a high-performance kernel to run on
1406		- new Loongson 3 machines only, please say 'Y' here.
	1411	+ new Loongson-3 machines only, please say 'Y' here.
	1412	+
	1413	+config CPU_LOONGSON3_WORKAROUNDS
	1414	+ bool "Old Loongson-3 LLSC Workarounds"
	1415	+ default y if SMP
	1416	+ depends on CPU_LOONGSON64
	1417	+ help
	1418	+ Loongson-3 processors have the llsc issues which require workarounds.
	1419	+ Without workarounds the system may hang unexpectedly.
	1420	+
	1421	+ Newer Loongson-3 will fix these issues and no workarounds are needed.
	1422	+ The workarounds have no significant side effect on them but may
	1423	+ decrease the performance of the system so this option should be
	1424	+ disabled unless the kernel is intended to be run on old systems.
	1425	+
	1426	+ If unsure, please say Y.
	1427	+
	1428	+config CPU_LOONGSON3_CPUCFG_EMULATION
	1429	+ bool "Emulate the CPUCFG instruction on older Loongson cores"
	1430	+ default y
	1431	+ depends on CPU_LOONGSON64
	1432	+ help
	1433	+ Loongson-3A R4 and newer have the CPUCFG instruction available for
	1434	+ userland to query CPU capabilities, much like CPUID on x86. This
	1435	+ option provides emulation of the instruction on older Loongson
	1436	+ cores, back to Loongson-3A1000.
	1437	+
	1438	+ If unsure, please say Y.
1407	1439
1408	1440	config CPU_LOONGSON2E
1409	1441	bool "Loongson 2E"
1410	1442	depends on SYS_HAS_CPU_LOONGSON2E
1411		- select CPU_LOONGSON2
	1443	+ select CPU_LOONGSON2EF
1412	1444	help
1413	1445	The Loongson 2E processor implements the MIPS III instruction set
1414	1446	with many extensions.
..	..	@@ -1419,7 +1451,7 @@
1419	1451	config CPU_LOONGSON2F
1420	1452	bool "Loongson 2F"
1421	1453	depends on SYS_HAS_CPU_LOONGSON2F
1422		- select CPU_LOONGSON2
	1454	+ select CPU_LOONGSON2EF
1423	1455	select GPIOLIB
1424	1456	help
1425	1457	The Loongson 2F processor implements the MIPS III instruction set
..	..	@@ -1432,7 +1464,7 @@
1432	1464	config CPU_LOONGSON1B
1433	1465	bool "Loongson 1B"
1434	1466	depends on SYS_HAS_CPU_LOONGSON1B
1435		- select CPU_LOONGSON1
	1467	+ select CPU_LOONGSON32
1436	1468	select LEDS_GPIO_REGISTER
1437	1469	help
1438	1470	The Loongson 1B is a 32-bit SoC, which implements the MIPS32
..	..	@@ -1442,7 +1474,7 @@
1442	1474	config CPU_LOONGSON1C
1443	1475	bool "Loongson 1C"
1444	1476	depends on SYS_HAS_CPU_LOONGSON1C
1445		- select CPU_LOONGSON1
	1477	+ select CPU_LOONGSON32
1446	1478	select LEDS_GPIO_REGISTER
1447	1479	help
1448	1480	The Loongson 1C is a 32-bit SoC, which implements the MIPS32
..	..	@@ -1481,14 +1513,29 @@
1481	1513	specific type of processor in your system, choose those that one
1482	1514	otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
1483	1515
1484		-config CPU_MIPS32_R6
1485		- bool "MIPS32 Release 6"
1486		- depends on SYS_HAS_CPU_MIPS32_R6
	1516	+config CPU_MIPS32_R5
	1517	+ bool "MIPS32 Release 5"
	1518	+ depends on SYS_HAS_CPU_MIPS32_R5
1487	1519	select CPU_HAS_PREFETCH
1488	1520	select CPU_SUPPORTS_32BIT_KERNEL
1489	1521	select CPU_SUPPORTS_HIGHMEM
1490	1522	select CPU_SUPPORTS_MSA
1491		- select GENERIC_CSUM
	1523	+ select HAVE_KVM
	1524	+ select MIPS_O32_FP64_SUPPORT
	1525	+ help
	1526	+ Choose this option to build a kernel for release 5 or later of the
	1527	+ MIPS32 architecture. New MIPS processors, starting with the Warrior
	1528	+ family, are based on a MIPS32r5 processor. If you own an older
	1529	+ processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
	1530	+
	1531	+config CPU_MIPS32_R6
	1532	+ bool "MIPS32 Release 6"
	1533	+ depends on SYS_HAS_CPU_MIPS32_R6
	1534	+ select CPU_HAS_PREFETCH
	1535	+ select CPU_NO_LOAD_STORE_LR
	1536	+ select CPU_SUPPORTS_32BIT_KERNEL
	1537	+ select CPU_SUPPORTS_HIGHMEM
	1538	+ select CPU_SUPPORTS_MSA
1492	1539	select HAVE_KVM
1493	1540	select MIPS_O32_FP64_SUPPORT
1494	1541	help
..	..	@@ -1533,15 +1580,33 @@
1533	1580	specific type of processor in your system, choose those that one
1534	1581	otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
1535	1582
1536		-config CPU_MIPS64_R6
1537		- bool "MIPS64 Release 6"
1538		- depends on SYS_HAS_CPU_MIPS64_R6
	1583	+config CPU_MIPS64_R5
	1584	+ bool "MIPS64 Release 5"
	1585	+ depends on SYS_HAS_CPU_MIPS64_R5
1539	1586	select CPU_HAS_PREFETCH
1540	1587	select CPU_SUPPORTS_32BIT_KERNEL
1541	1588	select CPU_SUPPORTS_64BIT_KERNEL
1542	1589	select CPU_SUPPORTS_HIGHMEM
	1590	+ select CPU_SUPPORTS_HUGEPAGES
1543	1591	select CPU_SUPPORTS_MSA
1544		- select GENERIC_CSUM
	1592	+ select MIPS_O32_FP64_SUPPORT if 32BIT \|\| MIPS32_O32
	1593	+ select HAVE_KVM
	1594	+ help
	1595	+ Choose this option to build a kernel for release 5 or later of the
	1596	+ MIPS64 architecture. This is a intermediate MIPS architecture
	1597	+ release partly implementing release 6 features. Though there is no
	1598	+ any hardware known to be based on this release.
	1599	+
	1600	+config CPU_MIPS64_R6
	1601	+ bool "MIPS64 Release 6"
	1602	+ depends on SYS_HAS_CPU_MIPS64_R6
	1603	+ select CPU_HAS_PREFETCH
	1604	+ select CPU_NO_LOAD_STORE_LR
	1605	+ select CPU_SUPPORTS_32BIT_KERNEL
	1606	+ select CPU_SUPPORTS_64BIT_KERNEL
	1607	+ select CPU_SUPPORTS_HIGHMEM
	1608	+ select CPU_SUPPORTS_HUGEPAGES
	1609	+ select CPU_SUPPORTS_MSA
1545	1610	select MIPS_O32_FP64_SUPPORT if 32BIT \|\| MIPS32_O32
1546	1611	select HAVE_KVM
1547	1612	help
..	..	@@ -1550,10 +1615,32 @@
1550	1615	family, are based on a MIPS64r6 processor. If you own an older
1551	1616	processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
1552	1617
	1618	+config CPU_P5600
	1619	+ bool "MIPS Warrior P5600"
	1620	+ depends on SYS_HAS_CPU_P5600
	1621	+ select CPU_HAS_PREFETCH
	1622	+ select CPU_SUPPORTS_32BIT_KERNEL
	1623	+ select CPU_SUPPORTS_HIGHMEM
	1624	+ select CPU_SUPPORTS_MSA
	1625	+ select CPU_SUPPORTS_CPUFREQ
	1626	+ select CPU_MIPSR2_IRQ_VI
	1627	+ select CPU_MIPSR2_IRQ_EI
	1628	+ select HAVE_KVM
	1629	+ select MIPS_O32_FP64_SUPPORT
	1630	+ help
	1631	+ Choose this option to build a kernel for MIPS Warrior P5600 CPU.
	1632	+ It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
	1633	+ MMU with two-levels TLB, UCA, MSA, MDU core level features and system
	1634	+ level features like up to six P5600 calculation cores, CM2 with L2
	1635	+ cache, IOCU/IOMMU (though might be unused depending on the system-
	1636	+ specific IP core configuration), GIC, CPC, virtualisation module,
	1637	+ eJTAG and PDtrace.
	1638	+
1553	1639	config CPU_R3000
1554	1640	bool "R3000"
1555	1641	depends on SYS_HAS_CPU_R3000
1556	1642	select CPU_HAS_WB
	1643	+ select CPU_R3K_TLB
1557	1644	select CPU_SUPPORTS_32BIT_KERNEL
1558	1645	select CPU_SUPPORTS_HIGHMEM
1559	1646	help
..	..	@@ -1568,6 +1655,7 @@
1568	1655	bool "R39XX"
1569	1656	depends on SYS_HAS_CPU_TX39XX
1570	1657	select CPU_SUPPORTS_32BIT_KERNEL
	1658	+ select CPU_R3K_TLB
1571	1659
1572	1660	config CPU_VR41XX
1573	1661	bool "R41xx"
..	..	@@ -1579,14 +1667,6 @@
1579	1667	Only choose this option if you have one of these processors as a
1580	1668	kernel built with this option will not run on any other type of
1581	1669	processor or vice versa.
1582		-
1583		-config CPU_R4300
1584		- bool "R4300"
1585		- depends on SYS_HAS_CPU_R4300
1586		- select CPU_SUPPORTS_32BIT_KERNEL
1587		- select CPU_SUPPORTS_64BIT_KERNEL
1588		- help
1589		- MIPS Technologies R4300-series processors.
1590	1670
1591	1671	config CPU_R4X00
1592	1672	bool "R4x00"
..	..	@@ -1615,13 +1695,6 @@
1615	1695	help
1616	1696	MIPS Technologies R5000-series processors other than the Nevada.
1617	1697
1618		-config CPU_R5432
1619		- bool "R5432"
1620		- depends on SYS_HAS_CPU_R5432
1621		- select CPU_SUPPORTS_32BIT_KERNEL
1622		- select CPU_SUPPORTS_64BIT_KERNEL
1623		- select CPU_SUPPORTS_HUGEPAGES
1624		-
1625	1698	config CPU_R5500
1626	1699	bool "R5500"
1627	1700	depends on SYS_HAS_CPU_R5500
..	..	@@ -1640,15 +1713,6 @@
1640	1713	select CPU_SUPPORTS_HUGEPAGES
1641	1714	help
1642	1715	QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1643		-
1644		-config CPU_R8000
1645		- bool "R8000"
1646		- depends on SYS_HAS_CPU_R8000
1647		- select CPU_HAS_PREFETCH
1648		- select CPU_SUPPORTS_64BIT_KERNEL
1649		- help
1650		- MIPS Technologies R8000 processors. Note these processors are
1651		- uncommon and the support for them is incomplete.
1652	1716
1653	1717	config CPU_R10000
1654	1718	bool "R10000"
..	..	@@ -1748,7 +1812,8 @@
1748	1812	config CPU_MIPS32_3_5_FEATURES
1749	1813	bool "MIPS32 Release 3.5 Features"
1750	1814	depends on SYS_HAS_CPU_MIPS32_R3_5
1751		- depends on CPU_MIPS32_R2 \|\| CPU_MIPS32_R6
	1815	+ depends on CPU_MIPS32_R2 \|\| CPU_MIPS32_R5 \|\| CPU_MIPS32_R6 \|\| \
	1816	+ CPU_P5600
1752	1817	help
1753	1818	Choose this option to build a kernel for release 2 or later of the
1754	1819	MIPS32 architecture including features from the 3.5 release such as
..	..	@@ -1768,7 +1833,7 @@
1768	1833	config CPU_MIPS32_R5_FEATURES
1769	1834	bool "MIPS32 Release 5 Features"
1770	1835	depends on SYS_HAS_CPU_MIPS32_R5
1771		- depends on CPU_MIPS32_R2
	1836	+ depends on CPU_MIPS32_R2 \|\| CPU_MIPS32_R5 \|\| CPU_P5600
1772	1837	help
1773	1838	Choose this option to build a kernel for release 2 or later of the
1774	1839	MIPS32 architecture including features from release 5 such as
..	..	@@ -1827,6 +1892,7 @@
1827	1892	select HAVE_KERNEL_LZMA
1828	1893	select HAVE_KERNEL_LZO
1829	1894	select HAVE_KERNEL_XZ
	1895	+ select HAVE_KERNEL_ZSTD
1830	1896
1831	1897	config SYS_SUPPORTS_ZBOOT_UART16550
1832	1898	bool
..	..	@@ -1836,7 +1902,7 @@
1836	1902	bool
1837	1903	select SYS_SUPPORTS_ZBOOT
1838	1904
1839		-config CPU_LOONGSON2
	1905	+config CPU_LOONGSON2EF
1840	1906	bool
1841	1907	select CPU_SUPPORTS_32BIT_KERNEL
1842	1908	select CPU_SUPPORTS_64BIT_KERNEL
..	..	@@ -1844,10 +1910,10 @@
1844	1910	select CPU_SUPPORTS_HUGEPAGES
1845	1911	select ARCH_HAS_PHYS_TO_DMA
1846	1912
1847		-config CPU_LOONGSON1
	1913	+config CPU_LOONGSON32
1848	1914	bool
1849	1915	select CPU_MIPS32
1850		- select CPU_MIPSR1
	1916	+ select CPU_MIPSR2
1851	1917	select CPU_HAS_PREFETCH
1852	1918	select CPU_SUPPORTS_32BIT_KERNEL
1853	1919	select CPU_SUPPORTS_HIGHMEM
..	..	@@ -1877,7 +1943,7 @@
1877	1943	select SYS_SUPPORTS_HOTPLUG_CPU
1878	1944	select CPU_HAS_RIXI
1879	1945
1880		-config SYS_HAS_CPU_LOONGSON3
	1946	+config SYS_HAS_CPU_LOONGSON64
1881	1947	bool
1882	1948	select CPU_SUPPORTS_CPUFREQ
1883	1949	select CPU_HAS_RIXI
..	..	@@ -1889,7 +1955,6 @@
1889	1955	bool
1890	1956	select CPU_SUPPORTS_CPUFREQ
1891	1957	select CPU_SUPPORTS_ADDRWINCFG if 64BIT
1892		- select CPU_SUPPORTS_UNCACHED_ACCELERATED
1893	1958
1894	1959	config SYS_HAS_CPU_LOONGSON1B
1895	1960	bool
..	..	@@ -1908,9 +1973,11 @@
1908	1973
1909	1974	config SYS_HAS_CPU_MIPS32_R5
1910	1975	bool
	1976	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1911	1977
1912	1978	config SYS_HAS_CPU_MIPS32_R6
1913	1979	bool
	1980	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1914	1981
1915	1982	config SYS_HAS_CPU_MIPS64_R1
1916	1983	bool
..	..	@@ -1918,8 +1985,17 @@
1918	1985	config SYS_HAS_CPU_MIPS64_R2
1919	1986	bool
1920	1987
	1988	+config SYS_HAS_CPU_MIPS64_R5
	1989	+ bool
	1990	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
	1991	+
1921	1992	config SYS_HAS_CPU_MIPS64_R6
1922	1993	bool
	1994	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
	1995	+
	1996	+config SYS_HAS_CPU_P5600
	1997	+ bool
	1998	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1923	1999
1924	2000	config SYS_HAS_CPU_R3000
1925	2001	bool
..	..	@@ -1928,9 +2004,6 @@
1928	2004	bool
1929	2005
1930	2006	config SYS_HAS_CPU_VR41XX
1931		- bool
1932		-
1933		-config SYS_HAS_CPU_R4300
1934	2007	bool
1935	2008
1936	2009	config SYS_HAS_CPU_R4X00
..	..	@@ -1942,20 +2015,15 @@
1942	2015	config SYS_HAS_CPU_R5000
1943	2016	bool
1944	2017
1945		-config SYS_HAS_CPU_R5432
1946		- bool
1947		-
1948	2018	config SYS_HAS_CPU_R5500
1949	2019	bool
1950	2020
1951	2021	config SYS_HAS_CPU_NEVADA
1952	2022	bool
1953	2023
1954		-config SYS_HAS_CPU_R8000
1955		- bool
1956		-
1957	2024	config SYS_HAS_CPU_R10000
1958	2025	bool
	2026	+ select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
1959	2027
1960	2028	config SYS_HAS_CPU_RM7000
1961	2029	bool
..	..	@@ -1984,6 +2052,7 @@
1984	2052	config SYS_HAS_CPU_BMIPS5000
1985	2053	bool
1986	2054	select SYS_HAS_CPU_BMIPS
	2055	+ select ARCH_HAS_SYNC_DMA_FOR_CPU
1987	2056
1988	2057	config SYS_HAS_CPU_XLR
1989	2058	bool
..	..	@@ -2011,14 +2080,16 @@
2011	2080	#
2012	2081	config CPU_MIPS32
2013	2082	bool
2014		- default y if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2 \|\| CPU_MIPS32_R6
	2083	+ default y if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2 \|\| CPU_MIPS32_R5 \|\| \
	2084	+ CPU_MIPS32_R6 \|\| CPU_P5600
2015	2085
2016	2086	config CPU_MIPS64
2017	2087	bool
2018		- default y if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS64_R6
	2088	+ default y if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS64_R5 \|\| \
	2089	+ CPU_MIPS64_R6
2019	2090
2020	2091	#
2021		-# These two indicate the revision of the architecture, either Release 1 or Release 2
	2092	+# These indicate the revision of the architecture
2022	2093	#
2023	2094	config CPU_MIPSR1
2024	2095	bool
..	..	@@ -2028,16 +2099,36 @@
2028	2099	bool
2029	2100	default y if CPU_MIPS32_R2 \|\| CPU_MIPS64_R2 \|\| CPU_CAVIUM_OCTEON
2030	2101	select CPU_HAS_RIXI
	2102	+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
	2103	+ select MIPS_SPRAM
	2104	+
	2105	+config CPU_MIPSR5
	2106	+ bool
	2107	+ default y if CPU_MIPS32_R5 \|\| CPU_MIPS64_R5 \|\| CPU_P5600
	2108	+ select CPU_HAS_RIXI
	2109	+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
2031	2110	select MIPS_SPRAM
2032	2111
2033	2112	config CPU_MIPSR6
2034	2113	bool
2035	2114	default y if CPU_MIPS32_R6 \|\| CPU_MIPS64_R6
2036	2115	select CPU_HAS_RIXI
	2116	+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
2037	2117	select HAVE_ARCH_BITREVERSE
2038	2118	select MIPS_ASID_BITS_VARIABLE
2039	2119	select MIPS_CRC_SUPPORT
2040	2120	select MIPS_SPRAM
	2121	+
	2122	+config TARGET_ISA_REV
	2123	+ int
	2124	+ default 1 if CPU_MIPSR1
	2125	+ default 2 if CPU_MIPSR2
	2126	+ default 5 if CPU_MIPSR5
	2127	+ default 6 if CPU_MIPSR6
	2128	+ default 0
	2129	+ help
	2130	+ Reflects the ISA revision being targeted by the kernel build. This
	2131	+ is effectively the Kconfig equivalent of MIPS_ISA_REV.
2041	2132
2042	2133	config EVA
2043	2134	bool
..	..	@@ -2059,8 +2150,7 @@
2059	2150	bool
2060	2151	config CPU_SUPPORTS_HUGEPAGES
2061	2152	bool
2062		-config CPU_SUPPORTS_UNCACHED_ACCELERATED
2063		- bool
	2153	+ depends on !(32BIT && (PHYS_ADDR_T_64BIT \|\| EVA))
2064	2154	config MIPS_PGD_C0_CONTEXT
2065	2155	bool
2066	2156	default y if 64BIT && (CPU_MIPSR2 \|\| CPU_MIPSR6) && !CPU_XLP
..	..	@@ -2069,8 +2159,8 @@
2069	2159	# Set to y for ptrace access to watch registers.
2070	2160	#
2071	2161	config HARDWARE_WATCHPOINTS
2072		- bool
2073		- default y if CPU_MIPSR1 \|\| CPU_MIPSR2 \|\| CPU_MIPSR6
	2162	+ bool
	2163	+ default y if CPU_MIPSR1 \|\| CPU_MIPSR2 \|\| CPU_MIPSR6
2074	2164
2075	2165	menu "Kernel type"
2076	2166
..	..	@@ -2099,6 +2189,7 @@
2099	2189
2100	2190	config KVM_GUEST
2101	2191	bool "KVM Guest Kernel"
	2192	+ depends on CPU_MIPS32_R2
2102	2193	depends on BROKEN_ON_SMP
2103	2194	help
2104	2195	Select this option if building a guest kernel for KVM (Trap & Emulate)
..	..	@@ -2132,22 +2223,22 @@
2132	2223
2133	2224	config PAGE_SIZE_4KB
2134	2225	bool "4kB"
2135		- depends on !CPU_LOONGSON2 && !CPU_LOONGSON3
	2226	+ depends on !CPU_LOONGSON2EF && !CPU_LOONGSON64
2136	2227	help
2137		- This option select the standard 4kB Linux page size. On some
2138		- R3000-family processors this is the only available page size. Using
2139		- 4kB page size will minimize memory consumption and is therefore
2140		- recommended for low memory systems.
	2228	+ This option select the standard 4kB Linux page size. On some
	2229	+ R3000-family processors this is the only available page size. Using
	2230	+ 4kB page size will minimize memory consumption and is therefore
	2231	+ recommended for low memory systems.
2141	2232
2142	2233	config PAGE_SIZE_8KB
2143	2234	bool "8kB"
2144		- depends on CPU_R8000 \|\| CPU_CAVIUM_OCTEON
	2235	+ depends on CPU_CAVIUM_OCTEON
2145	2236	depends on !MIPS_VA_BITS_48
2146	2237	help
2147	2238	Using 8kB page size will result in higher performance kernel at
2148	2239	the price of higher memory consumption. This option is available
2149		- only on R8000 and cnMIPS processors. Note that you will need a
2150		- suitable Linux distribution to support this.
	2240	+ only on cnMIPS processors. Note that you will need a suitable Linux
	2241	+ distribution to support this.
2151	2242
2152	2243	config PAGE_SIZE_16KB
2153	2244	bool "16kB"
..	..	@@ -2187,7 +2278,7 @@
2187	2278	default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB
2188	2279	range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2189	2280	default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB
2190		- range 11 64
	2281	+ range 0 64
2191	2282	default "11"
2192	2283	help
2193	2284	The kernel memory allocator divides physically contiguous memory
..	..	@@ -2238,15 +2329,39 @@
2238	2329
2239	2330	config CPU_GENERIC_DUMP_TLB
2240	2331	bool
2241		- default y if !(CPU_R3000 \|\| CPU_R8000 \|\| CPU_TX39XX)
	2332	+ default y if !(CPU_R3000 \|\| CPU_TX39XX)
	2333	+
	2334	+config MIPS_FP_SUPPORT
	2335	+ bool "Floating Point support" if EXPERT
	2336	+ default y
	2337	+ help
	2338	+ Select y to include support for floating point in the kernel
	2339	+ including initialization of FPU hardware, FP context save & restore
	2340	+ and emulation of an FPU where necessary. Without this support any
	2341	+ userland program attempting to use floating point instructions will
	2342	+ receive a SIGILL.
	2343	+
	2344	+ If you know that your userland will not attempt to use floating point
	2345	+ instructions then you can say n here to shrink the kernel a little.
	2346	+
	2347	+ If unsure, say y.
	2348	+
	2349	+config CPU_R2300_FPU
	2350	+ bool
	2351	+ depends on MIPS_FP_SUPPORT
	2352	+ default y if CPU_R3000 \|\| CPU_TX39XX
	2353	+
	2354	+config CPU_R3K_TLB
	2355	+ bool
2242	2356
2243	2357	config CPU_R4K_FPU
2244	2358	bool
2245		- default y if !(CPU_R3000 \|\| CPU_TX39XX)
	2359	+ depends on MIPS_FP_SUPPORT
	2360	+ default y if !CPU_R2300_FPU
2246	2361
2247	2362	config CPU_R4K_CACHE_TLB
2248	2363	bool
2249		- default y if !(CPU_R3000 \|\| CPU_R8000 \|\| CPU_SB1 \|\| CPU_TX39XX \|\| CPU_CAVIUM_OCTEON)
	2364	+ default y if !(CPU_R3K_TLB \|\| CPU_SB1 \|\| CPU_CAVIUM_OCTEON)
2250	2365
2251	2366	config MIPS_MT_SMP
2252	2367	bool "MIPS MT SMP support (1 TC on each available VPE)"
..	..	@@ -2294,6 +2409,7 @@
2294	2409	config MIPSR2_TO_R6_EMULATOR
2295	2410	bool "MIPS R2-to-R6 emulator"
2296	2411	depends on CPU_MIPSR6
	2412	+ depends on MIPS_FP_SUPPORT
2297	2413	default y
2298	2414	help
2299	2415	Choose this option if you want to run non-R6 MIPS userland code.
..	..	@@ -2408,7 +2524,6 @@
2408	2524	depends on CPU_SB1 && CPU_SB1_PASS_2
2409	2525	default y
2410	2526
2411		-
2412	2527	choice
2413	2528	prompt "SmartMIPS or microMIPS ASE support"
2414	2529
..	..	@@ -2441,6 +2556,7 @@
2441	2556	config CPU_HAS_MSA
2442	2557	bool "Support for the MIPS SIMD Architecture"
2443	2558	depends on CPU_SUPPORTS_MSA
	2559	+ depends on MIPS_FP_SUPPORT
2444	2560	depends on 64BIT \|\| MIPS_O32_FP64_SUPPORT
2445	2561	help
2446	2562	MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers
..	..	@@ -2459,8 +2575,23 @@
2459	2575	config XKS01
2460	2576	bool
2461	2577
	2578	+config CPU_HAS_DIEI
	2579	+ depends on !CPU_DIEI_BROKEN
	2580	+ bool
	2581	+
	2582	+config CPU_DIEI_BROKEN
	2583	+ bool
	2584	+
2462	2585	config CPU_HAS_RIXI
2463	2586	bool
	2587	+
	2588	+config CPU_NO_LOAD_STORE_LR
	2589	+ bool
	2590	+ help
	2591	+ CPU lacks support for unaligned load and store instructions:
	2592	+ LWL, LWR, SWL, SWR (Load/store word left/right).
	2593	+ LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
	2594	+ systems).
2464	2595
2465	2596	#
2466	2597	# Vectored interrupt mode is an R2 feature
..	..	@@ -2492,10 +2623,13 @@
2492	2623	config CPU_R4400_WORKAROUNDS
2493	2624	bool
2494	2625
	2626	+config CPU_R4X00_BUGS64
	2627	+ bool
	2628	+ default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1)
	2629	+
2495	2630	config MIPS_ASID_SHIFT
2496	2631	int
2497	2632	default 6 if CPU_R3000 \|\| CPU_TX39XX
2498		- default 4 if CPU_R8000
2499	2633	default 0
2500	2634
2501	2635	config MIPS_ASID_BITS
..	..	@@ -2508,6 +2642,76 @@
2508	2642	bool
2509	2643
2510	2644	config MIPS_CRC_SUPPORT
	2645	+ bool
	2646	+
	2647	+# R4600 erratum. Due to the lack of errata information the exact
	2648	+# technical details aren't known. I've experimentally found that disabling
	2649	+# interrupts during indexed I-cache flushes seems to be sufficient to deal
	2650	+# with the issue.
	2651	+config WAR_R4600_V1_INDEX_ICACHEOP
	2652	+ bool
	2653	+
	2654	+# Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata:
	2655	+#
	2656	+# 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
	2657	+# Hit_Invalidate_D and Create_Dirty_Excl_D should only be
	2658	+# executed if there is no other dcache activity. If the dcache is
	2659	+# accessed for another instruction immeidately preceding when these
	2660	+# cache instructions are executing, it is possible that the dcache
	2661	+# tag match outputs used by these cache instructions will be
	2662	+# incorrect. These cache instructions should be preceded by at least
	2663	+# four instructions that are not any kind of load or store
	2664	+# instruction.
	2665	+#
	2666	+# This is not allowed: lw
	2667	+# nop
	2668	+# nop
	2669	+# nop
	2670	+# cache Hit_Writeback_Invalidate_D
	2671	+#
	2672	+# This is allowed: lw
	2673	+# nop
	2674	+# nop
	2675	+# nop
	2676	+# nop
	2677	+# cache Hit_Writeback_Invalidate_D
	2678	+config WAR_R4600_V1_HIT_CACHEOP
	2679	+ bool
	2680	+
	2681	+# Writeback and invalidate the primary cache dcache before DMA.
	2682	+#
	2683	+# R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
	2684	+# Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
	2685	+# operate correctly if the internal data cache refill buffer is empty. These
	2686	+# CACHE instructions should be separated from any potential data cache miss
	2687	+# by a load instruction to an uncached address to empty the response buffer."
	2688	+# (Revision 2.0 device errata from IDT available on https://www.idt.com/
	2689	+# in .pdf format.)
	2690	+config WAR_R4600_V2_HIT_CACHEOP
	2691	+ bool
	2692	+
	2693	+# From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
	2694	+# the line which this instruction itself exists, the following
	2695	+# operation is not guaranteed."
	2696	+#
	2697	+# Workaround: do two phase flushing for Index_Invalidate_I
	2698	+config WAR_TX49XX_ICACHE_INDEX_INV
	2699	+ bool
	2700	+
	2701	+# The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
	2702	+# opposes it being called that) where invalid instructions in the same
	2703	+# I-cache line worth of instructions being fetched may case spurious
	2704	+# exceptions.
	2705	+config WAR_ICACHE_REFILLS
	2706	+ bool
	2707	+
	2708	+# On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
	2709	+# may cause ll / sc and lld / scd sequences to execute non-atomically.
	2710	+config WAR_R10000_LLSC
	2711	+ bool
	2712	+
	2713	+# 34K core erratum: "Problems Executing the TLBR Instruction"
	2714	+config WAR_MIPS34K_MISSED_ITLB
2511	2715	bool
2512	2716
2513	2717	#
..	..	@@ -2525,7 +2729,8 @@
2525	2729	#
2526	2730	config HIGHMEM
2527	2731	bool "High Memory Support"
2528		- depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA && !PREEMPT_RT_FULL
	2732	+ depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM && !CPU_MIPS32_3_5_EVA
	2733	+ select KMAP_LOCAL
2529	2734
2530	2735	config CPU_SUPPORTS_HIGHMEM
2531	2736	bool
..	..	@@ -2551,20 +2756,11 @@
2551	2756
2552	2757	config ARCH_FLATMEM_ENABLE
2553	2758	def_bool y
2554		- depends on !NUMA && !CPU_LOONGSON2
2555		-
2556		-config ARCH_DISCONTIGMEM_ENABLE
2557		- bool
2558		- default y if SGI_IP27
2559		- help
2560		- Say Y to support efficient handling of discontiguous physical memory,
2561		- for architectures which are either NUMA (Non-Uniform Memory Access)
2562		- or have huge holes in the physical address space for other reasons.
2563		- See <file:Documentation/vm/numa.rst> for more.
	2759	+ depends on !NUMA && !CPU_LOONGSON2EF
2564	2760
2565	2761	config ARCH_SPARSEMEM_ENABLE
2566	2762	bool
2567		- select SPARSEMEM_STATIC
	2763	+ select SPARSEMEM_STATIC if !SGI_IP27
2568	2764
2569	2765	config NUMA
2570	2766	bool "NUMA Support"
..	..	@@ -2573,15 +2769,27 @@
2573	2769	Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2574	2770	Access). This option improves performance on systems with more
2575	2771	than two nodes; on two node systems it is generally better to
2576		- leave it disabled; on single node systems disable this option
	2772	+ leave it disabled; on single node systems leave this option
2577	2773	disabled.
2578	2774
2579	2775	config SYS_SUPPORTS_NUMA
2580	2776	bool
2581	2777
	2778	+config HAVE_SETUP_PER_CPU_AREA
	2779	+ def_bool y
	2780	+ depends on NUMA
	2781	+
	2782	+config NEED_PER_CPU_EMBED_FIRST_CHUNK
	2783	+ def_bool y
	2784	+ depends on NUMA
	2785	+
2582	2786	config RELOCATABLE
2583	2787	bool "Relocatable kernel"
2584		- depends on SYS_SUPPORTS_RELOCATABLE && (CPU_MIPS32_R2 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS32_R6 \|\| CPU_MIPS64_R6 \|\| CAVIUM_OCTEON_SOC)
	2788	+ depends on SYS_SUPPORTS_RELOCATABLE
	2789	+ depends on CPU_MIPS32_R2 \|\| CPU_MIPS64_R2 \|\| \
	2790	+ CPU_MIPS32_R5 \|\| CPU_MIPS64_R5 \|\| \
	2791	+ CPU_MIPS32_R6 \|\| CPU_MIPS64_R6 \|\| \
	2792	+ CPU_P5600 \|\| CAVIUM_OCTEON_SOC
2585	2793	help
2586	2794	This builds a kernel image that retains relocation information
2587	2795	so it can be loaded someplace besides the default 1MB.
..	..	@@ -2593,7 +2801,7 @@
2593	2801	depends on RELOCATABLE
2594	2802	range 0x0 0x01000000
2595	2803	default "0x00100000"
2596		- ---help---
	2804	+ help
2597	2805	A table of relocation data will be appended to the kernel binary
2598	2806	and parsed at boot to fix up the relocated kernel.
2599	2807
..	..	@@ -2607,17 +2815,17 @@
2607	2815	config RANDOMIZE_BASE
2608	2816	bool "Randomize the address of the kernel image"
2609	2817	depends on RELOCATABLE
2610		- ---help---
2611		- Randomizes the physical and virtual address at which the
2612		- kernel image is loaded, as a security feature that
2613		- deters exploit attempts relying on knowledge of the location
2614		- of kernel internals.
	2818	+ help
	2819	+ Randomizes the physical and virtual address at which the
	2820	+ kernel image is loaded, as a security feature that
	2821	+ deters exploit attempts relying on knowledge of the location
	2822	+ of kernel internals.
2615	2823
2616		- Entropy is generated using any coprocessor 0 registers available.
	2824	+ Entropy is generated using any coprocessor 0 registers available.
2617	2825
2618		- The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
	2826	+ The kernel will be offset by up to RANDOMIZE_BASE_MAX_OFFSET.
2619	2827
2620		- If unsure, say N.
	2828	+ If unsure, say N.
2621	2829
2622	2830	config RANDOMIZE_BASE_MAX_OFFSET
2623	2831	hex "Maximum kASLR offset" if EXPERT
..	..	@@ -2625,7 +2833,7 @@
2625	2833	range 0x0 0x40000000 if EVA \|\| 64BIT
2626	2834	range 0x0 0x08000000
2627	2835	default "0x01000000"
2628		- ---help---
	2836	+ help
2629	2837	When kASLR is active, this provides the maximum offset that will
2630	2838	be applied to the kernel image. It should be set according to the
2631	2839	amount of physical RAM available in the target system minus
..	..	@@ -2641,11 +2849,22 @@
2641	2849
2642	2850	config HW_PERF_EVENTS
2643	2851	bool "Enable hardware performance counter support for perf events"
2644		- depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 \|\| CPU_MIPS64 \|\| CPU_R10000 \|\| CPU_SB1 \|\| CPU_CAVIUM_OCTEON \|\| CPU_XLP \|\| CPU_LOONGSON3)
	2852	+ depends on PERF_EVENTS && !OPROFILE && (CPU_MIPS32 \|\| CPU_MIPS64 \|\| CPU_R10000 \|\| CPU_SB1 \|\| CPU_CAVIUM_OCTEON \|\| CPU_XLP \|\| CPU_LOONGSON64)
2645	2853	default y
2646	2854	help
2647	2855	Enable hardware performance counter support for perf events. If
2648	2856	disabled, perf events will use software events only.
	2857	+
	2858	+config DMI
	2859	+ bool "Enable DMI scanning"
	2860	+ depends on MACH_LOONGSON64
	2861	+ select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
	2862	+ default y
	2863	+ help
	2864	+ Enabled scanning of DMI to identify machine quirks. Say Y
	2865	+ here unless you have verified that your setup is not
	2866	+ affected by entries in the DMI blacklist. Required by PNP
	2867	+ BIOS code.
2649	2868
2650	2869	config SMP
2651	2870	bool "Multi-Processing support"
..	..	@@ -2665,7 +2884,7 @@
2665	2884	Y to "Enhanced Real Time Clock Support", below.
2666	2885
2667	2886	See also the SMP-HOWTO available at
2668		- <http://www.tldp.org/docs.html#howto>.
	2887	+ <https://www.tldp.org/docs.html#howto>.
2669	2888
2670	2889	If you don't know what to do here, say N.
2671	2890
..	..	@@ -2747,7 +2966,7 @@
2747	2966	prompt "Timer frequency"
2748	2967	default HZ_250
2749	2968	help
2750		- Allows the configuration of the timer frequency.
	2969	+ Allows the configuration of the timer frequency.
2751	2970
2752	2971	config HZ_24
2753	2972	bool "24 HZ" if SYS_SUPPORTS_24HZ \|\| SYS_SUPPORTS_ARBIT_HZ
..	..	@@ -2863,25 +3082,8 @@
2863	3082	specified in the "crashkernel=YM@XM" command line boot parameter
2864	3083	passed to the panic-ed kernel).
2865	3084
2866		-config SECCOMP
2867		- bool "Enable seccomp to safely compute untrusted bytecode"
2868		- depends on PROC_FS
2869		- default y
2870		- help
2871		- This kernel feature is useful for number crunching applications
2872		- that may need to compute untrusted bytecode during their
2873		- execution. By using pipes or other transports made available to
2874		- the process as file descriptors supporting the read/write
2875		- syscalls, it's possible to isolate those applications in
2876		- their own address space using seccomp. Once seccomp is
2877		- enabled via /proc/<pid>/seccomp, it cannot be disabled
2878		- and the task is only allowed to execute a few safe syscalls
2879		- defined by each seccomp mode.
2880		-
2881		- If unsure, say Y. Only embedded should say N here.
2882		-
2883	3085	config MIPS_O32_FP64_SUPPORT
2884		- bool "Support for O32 binaries using 64-bit FP"
	3086	+ bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2885	3087	depends on 32BIT \|\| MIPS32_O32
2886	3088	help
2887	3089	When this is enabled, the kernel will support use of 64-bit floating
..	..	@@ -2908,6 +3110,9 @@
2908	3110	select OF
2909	3111	select OF_EARLY_FLATTREE
2910	3112	select IRQ_DOMAIN
	3113	+
	3114	+config UHI_BOOT
	3115	+ bool
2911	3116
2912	3117	config BUILTIN_DTB
2913	3118	bool
..	..	@@ -2956,7 +3161,7 @@
2956	3161	choice
2957	3162	prompt "Kernel command line type" if !CMDLINE_OVERRIDE
2958	3163	default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
2959		- !MIPS_MALTA && \
	3164	+ !MACH_LOONGSON64 && !MIPS_MALTA && \
2960	3165	!CAVIUM_OCTEON_SOC
2961	3166	default MIPS_CMDLINE_FROM_BOOTLOADER
2962	3167
..	..	@@ -2986,10 +3191,6 @@
2986	3191	bool
2987	3192	default y
2988	3193
2989		-config HAVE_LATENCYTOP_SUPPORT
2990		- bool
2991		- default y
2992		-
2993	3194	config PGTABLE_LEVELS
2994	3195	int
2995	3196	default 4 if PAGE_SIZE_4KB && MIPS_VA_BITS_48
..	..	@@ -3001,47 +3202,14 @@
3001	3202
3002	3203	menu "Bus options (PCI, PCMCIA, EISA, ISA, TC)"
3003	3204
3004		-config HW_HAS_EISA
3005		- bool
3006		-config HW_HAS_PCI
3007		- bool
3008		-
3009		-config PCI
3010		- bool "Support for PCI controller"
3011		- depends on HW_HAS_PCI
3012		- select PCI_DOMAINS
3013		- help
3014		- Find out whether you have a PCI motherboard. PCI is the name of a
3015		- bus system, i.e. the way the CPU talks to the other stuff inside
3016		- your box. Other bus systems are ISA, EISA, or VESA. If you have PCI,
3017		- say Y, otherwise N.
3018		-
3019		-config HT_PCI
3020		- bool "Support for HT-linked PCI"
3021		- default y
3022		- depends on CPU_LOONGSON3
3023		- select PCI
3024		- select PCI_DOMAINS
3025		- help
3026		- Loongson family machines use Hyper-Transport bus for inter-core
3027		- connection and device connection. The PCI bus is a subordinate
3028		- linked at HT. Choose Y for Loongson-3 based machines.
3029		-
3030		-config PCI_DOMAINS
3031		- bool
3032		-
3033		-config PCI_DOMAINS_GENERIC
3034		- bool
3035		-
3036	3205	config PCI_DRIVERS_GENERIC
3037		- select PCI_DOMAINS_GENERIC if PCI_DOMAINS
	3206	+ select PCI_DOMAINS_GENERIC if PCI
3038	3207	bool
3039	3208
3040	3209	config PCI_DRIVERS_LEGACY
3041	3210	def_bool !PCI_DRIVERS_GENERIC
3042	3211	select NO_GENERIC_PCI_IOPORT_MAP
3043		-
3044		-source "drivers/pci/Kconfig"
	3212	+ select PCI_DOMAINS if PCI
3045	3213
3046	3214	#
3047	3215	# ISA support is now enabled via select. Too many systems still have the one
..	..	@@ -3050,26 +3218,6 @@
3050	3218	#
3051	3219	config ISA
3052	3220	bool
3053		-
3054		-config EISA
3055		- bool "EISA support"
3056		- depends on HW_HAS_EISA
3057		- select ISA
3058		- select GENERIC_ISA_DMA
3059		- ---help---
3060		- The Extended Industry Standard Architecture (EISA) bus was
3061		- developed as an open alternative to the IBM MicroChannel bus.
3062		-
3063		- The EISA bus provided some of the features of the IBM MicroChannel
3064		- bus while maintaining backward compatibility with cards made for
3065		- the older ISA bus. The EISA bus saw limited use between 1988 and
3066		- 1995 when it was made obsolete by the PCI bus.
3067		-
3068		- Say Y here if you are building a kernel for an EISA-based machine.
3069		-
3070		- Otherwise, say N.
3071		-
3072		-source "drivers/eisa/Kconfig"
3073	3221
3074	3222	config TC
3075	3223	bool "TURBOchannel support"
..	..	@@ -3097,10 +3245,10 @@
3097	3245	default 15
3098	3246
3099	3247	config ARCH_MMAP_RND_COMPAT_BITS_MIN
3100		- default 8
	3248	+ default 8
3101	3249
3102	3250	config ARCH_MMAP_RND_COMPAT_BITS_MAX
3103		- default 15
	3251	+ default 15
3104	3252
3105	3253	config I8253
3106	3254	bool
..	..	@@ -3113,21 +3261,6 @@
3113	3261
3114	3262	config ZONE_DMA32
3115	3263	bool
3116		-
3117		-source "drivers/pcmcia/Kconfig"
3118		-
3119		-config HAS_RAPIDIO
3120		- bool
3121		- default n
3122		-
3123		-config RAPIDIO
3124		- tristate "RapidIO support"
3125		- depends on HAS_RAPIDIO \|\| PCI
3126		- help
3127		- If you say Y here, the kernel will include drivers and
3128		- infrastructure code to support RapidIO interconnect devices.
3129		-
3130		-source "drivers/rapidio/Kconfig"
3131	3264
3132	3265	endmenu
3133	3266
..	..	@@ -3207,3 +3340,5 @@
3207	3340	source "drivers/firmware/Kconfig"
3208	3341
3209	3342	source "arch/mips/kvm/Kconfig"
	3343	+
	3344	+source "arch/mips/vdso/Kconfig"