hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/arm64/lib/Makefile
....@@ -1,32 +1,20 @@
11 # SPDX-License-Identifier: GPL-2.0
22 lib-y := clear_user.o delay.o copy_from_user.o \
33 copy_to_user.o copy_in_user.o copy_page.o \
4
- clear_page.o memchr.o memcpy.o memmove.o memset.o \
5
- memcmp.o strcmp.o strncmp.o strlen.o strnlen.o \
6
- strchr.o strrchr.o tishift.o
4
+ clear_page.o csum.o memchr.o memcpy.o memmove.o \
5
+ memset.o memcmp.o strcmp.o strncmp.o strlen.o \
6
+ strnlen.o strchr.o strrchr.o tishift.o
77
8
-# Tell the compiler to treat all general purpose registers (with the
9
-# exception of the IP registers, which are already handled by the caller
10
-# in case of a PLT) as callee-saved, which allows for efficient runtime
11
-# patching of the bl instruction in the caller with an atomic instruction
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-# when supported by the CPU. Result and argument registers are handled
13
-# correctly, based on the function prototype.
14
-ifeq ($(CONFIG_LD_IS_LLD), y)
15
-# https://bugs.llvm.org/show_bug.cgi?id=35841
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-obj-$(CONFIG_ARM64_LSE_ATOMICS) += atomic_ll_sc.o
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-else
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-lib-$(CONFIG_ARM64_LSE_ATOMICS) += atomic_ll_sc.o
8
+ifeq ($(CONFIG_KERNEL_MODE_NEON), y)
9
+obj-$(CONFIG_XOR_BLOCKS) += xor-neon.o
10
+CFLAGS_REMOVE_xor-neon.o += -mgeneral-regs-only
11
+CFLAGS_xor-neon.o += -ffreestanding
1912 endif
20
-CFLAGS_atomic_ll_sc.o := -ffixed-x1 -ffixed-x2 \
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- -ffixed-x3 -ffixed-x4 -ffixed-x5 -ffixed-x6 \
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- -ffixed-x7 -fcall-saved-x8 -fcall-saved-x9 \
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- -fcall-saved-x10 -fcall-saved-x11 -fcall-saved-x12 \
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- -fcall-saved-x13 -fcall-saved-x14 -fcall-saved-x15 \
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- -fcall-saved-x18 -fomit-frame-pointer
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-CFLAGS_REMOVE_atomic_ll_sc.o := -pg
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-GCOV_PROFILE_atomic_ll_sc.o := n
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-KASAN_SANITIZE_atomic_ll_sc.o := n
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-KCOV_INSTRUMENT_atomic_ll_sc.o := n
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-UBSAN_SANITIZE_atomic_ll_sc.o := n
3113
3214 lib-$(CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE) += uaccess_flushcache.o
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+
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+obj-$(CONFIG_CRC32) += crc32.o
17
+
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+obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o
19
+
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+obj-$(CONFIG_ARM64_MTE) += mte.o